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Thu, 25 Jul 2024 22:08:11 -0700 (PDT) Received: from thinkpad ([220.158.156.199]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1fed7f99099sm22814675ad.247.2024.07.25.22.08.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Jul 2024 22:08:10 -0700 (PDT) Date: Fri, 26 Jul 2024 10:38:05 +0530 From: Manivannan Sadhasivam To: Jim Quinlan Cc: linux-pci@vger.kernel.org, Nicolas Saenz Julienne , Bjorn Helgaas , Lorenzo Pieralisi , Cyril Brulebois , Stanimir Varbanov , Krzysztof Kozlowski , bcm-kernel-feedback-list@broadcom.com, jim2101024@gmail.com, Florian Fainelli , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Rob Herring , "moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE" , "moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE" , open list Subject: Re: [PATCH v4 09/12] PCI: brcmstb: Refactor for chips with many regular inbound BARs Message-ID: <20240726050805.GC2628@thinkpad> References: <20240716213131.6036-1-james.quinlan@broadcom.com> <20240716213131.6036-10-james.quinlan@broadcom.com> <20240725045318.GJ2317@thinkpad> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: On Thu, Jul 25, 2024 at 04:29:56PM -0400, Jim Quinlan wrote: > On Thu, Jul 25, 2024 at 12:53 AM Manivannan Sadhasivam > wrote: > > > > On Tue, Jul 16, 2024 at 05:31:24PM -0400, Jim Quinlan wrote: > > > Previously, our chips provided three inbound "BARS" with fixed purposes: > > > the first was for mapping SoC internal registers, the second was for > > > memory, and the third was for memory but with the endian swapped. We > > > typically only used one of these BARs. > > > > > > Complicating that BARs usage was the fact that the PCIe HW would do a > > > baroque internal mapping of system memory, and concatenate the regions of > > > multiple memory controllers. > > > > > > Newer chips such as the 7712 and Cable Modem SOCs have taken a step forward > > > and now provide multiple inbound BARs. This works in concert with the > > > dma-ranges property, where each provided range becomes an inbound BAR. > > > > > > This commit provides support for these new chips and their multiple > > > inbound BARs but also keeps the legacy support for the older system. > > > > > > > BAR belongs to the endpoints not to the RC. How can the RC have 'BARs'? RC can > > only map endpoint BARs to MEM region. What you are referring to is 'MEM region' > > maybe? > > Agreed, it is confusing. Long story short, the HW team gave the > inbound windows the label "BAR". We will still have to use their > register names, Wow, such an inventive naming :) > e.g. PCIE_MISC_RC_BAR4_CONFIG_LO, but what I can do is change > for example "struct rc_bar" to "struct inbound_win" as well as make similar > changes to the code and function names. > > Let's assume you will be okay with my plan above; if not, please tell > me what you would prefer. > Yes please. Just keep BAR in the register name and use 'inbound_win' elsewhere. Even better, add a comment at the top of these register names to clarify that these refer to inbound windows. - Mani -- மணிவண்ணன் சதாசிவம்