From: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
To: linux-sound@vger.kernel.org
Cc: alsa-devel@alsa-project.org, tiwai@suse.de, broonie@kernel.org,
"Bjorn Helgaas" <bhelgaas@google.com>,
linux-pci@vger.kernel.org, "Fred Oh" <fred.oh@linux.intel.com>,
"Ranjani Sridharan" <ranjani.sridharan@linux.intel.com>,
"Bard Liao" <yung-chuan.liao@linux.intel.com>,
"Péter Ujfalusi" <peter.ujfalusi@linux.intel.com>,
"Pierre-Louis Bossart" <pierre-louis.bossart@linux.intel.com>
Subject: [PATCH v4 2/5] ASoC: SOF: Intel: add PTL specific power control register
Date: Fri, 2 Aug 2024 14:40:08 +0200 [thread overview]
Message-ID: <20240802124011.173820-3-pierre-louis.bossart@linux.intel.com> (raw)
In-Reply-To: <20240802124011.173820-1-pierre-louis.bossart@linux.intel.com>
From: Fred Oh <fred.oh@linux.intel.com>
PTL has some differences from MTL/LNL. Need to use different register
to power up.
Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
Reviewed-by: Bard Liao <yung-chuan.liao@linux.intel.com>
Reviewed-by: Péter Ujfalusi <peter.ujfalusi@linux.intel.com>
Signed-off-by: Fred Oh <fred.oh@linux.intel.com>
Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
---
sound/soc/sof/intel/mtl.c | 16 ++++++++++++++--
sound/soc/sof/intel/mtl.h | 2 ++
2 files changed, 16 insertions(+), 2 deletions(-)
diff --git a/sound/soc/sof/intel/mtl.c b/sound/soc/sof/intel/mtl.c
index 24dcd8a3098d..e767de085f04 100644
--- a/sound/soc/sof/intel/mtl.c
+++ b/sound/soc/sof/intel/mtl.c
@@ -245,6 +245,18 @@ int mtl_dsp_pre_fw_run(struct snd_sof_dev *sdev)
u32 cpa;
u32 pgs;
int ret;
+ u32 dsppwrctl;
+ u32 dsppwrsts;
+ const struct sof_intel_dsp_desc *chip;
+
+ chip = get_chip_info(sdev->pdata);
+ if (chip->hw_ip_version > SOF_INTEL_ACE_2_0) {
+ dsppwrctl = PTL_HFPWRCTL2;
+ dsppwrsts = PTL_HFPWRSTS2;
+ } else {
+ dsppwrctl = MTL_HFPWRCTL;
+ dsppwrsts = MTL_HFPWRSTS;
+ }
/* Set the DSP subsystem power on */
snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_HFDSSCS,
@@ -264,14 +276,14 @@ int mtl_dsp_pre_fw_run(struct snd_sof_dev *sdev)
}
/* Power up gated-DSP-0 domain in order to access the DSP shim register block. */
- snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_HFPWRCTL,
+ snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, dsppwrctl,
MTL_HFPWRCTL_WPDSPHPXPG, MTL_HFPWRCTL_WPDSPHPXPG);
usleep_range(1000, 1010);
/* poll with timeout to check if operation successful */
pgs = MTL_HFPWRSTS_DSPHPXPGS_MASK;
- ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, MTL_HFPWRSTS, dsphfpwrsts,
+ ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, dsppwrsts, dsphfpwrsts,
(dsphfpwrsts & pgs) == pgs,
HDA_DSP_REG_POLL_INTERVAL_US,
HDA_DSP_RESET_TIMEOUT_US);
diff --git a/sound/soc/sof/intel/mtl.h b/sound/soc/sof/intel/mtl.h
index 7acaa7e724f4..9ab4b21c960e 100644
--- a/sound/soc/sof/intel/mtl.h
+++ b/sound/soc/sof/intel/mtl.h
@@ -12,9 +12,11 @@
#define MTL_HFDSSCS_CPA_MASK BIT(24)
#define MTL_HFSNDWIE 0x114C
#define MTL_HFPWRCTL 0x1D18
+#define PTL_HFPWRCTL2 0x1D20
#define MTL_HfPWRCTL_WPIOXPG(x) BIT((x) + 8)
#define MTL_HFPWRCTL_WPDSPHPXPG BIT(0)
#define MTL_HFPWRSTS 0x1D1C
+#define PTL_HFPWRSTS2 0x1D24
#define MTL_HFPWRSTS_DSPHPXPGS_MASK BIT(0)
#define MTL_HFINTIPPTR 0x1108
#define MTL_IRQ_INTEN_L_HOST_IPC_MASK BIT(0)
--
2.43.0
next prev parent reply other threads:[~2024-08-02 12:40 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-08-02 12:40 [PATCH v4 0/5] ASoC/SOF/PCI/Intel: add PantherLake support Pierre-Louis Bossart
2024-08-02 12:40 ` [PATCH v4 1/5] ASoC: Intel: soc-acpi: add PTL match tables Pierre-Louis Bossart
2024-08-02 12:40 ` Pierre-Louis Bossart [this message]
2024-08-02 12:40 ` [PATCH v4 3/5] ASoC: SOF: Intel: add initial support for PTL Pierre-Louis Bossart
2024-08-02 12:40 ` [PATCH v4 4/5] ASoC: Intel: soc-acpi-intel-ptl-match: add rt711-sdca table Pierre-Louis Bossart
2024-08-02 12:40 ` [PATCH v4 5/5] ASoC: Intel: soc-acpi-intel-ptl-match: Add rt722 support Pierre-Louis Bossart
2024-08-02 22:22 ` [PATCH v4 0/5] ASoC/SOF/PCI/Intel: add PantherLake support Mark Brown
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