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From: Bjorn Helgaas <helgaas@kernel.org>
To: 412574090@163.com
Cc: ilpo.jarvinen@linux.intel.com, bhelgaas@google.com,
	linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org,
	xiongxin@kylinos.cn
Subject: Re: [PATCH] PCI: Add PCI_EXT_CAP_ID_PL_64GT define
Date: Thu, 8 Aug 2024 12:22:21 -0500	[thread overview]
Message-ID: <20240808172221.GA150885@bhelgaas> (raw)
In-Reply-To: <20240808023217.25673-1-412574090@163.com>

On Thu, Aug 08, 2024 at 10:32:17AM +0800, 412574090@163.com wrote:

You inadvertently trimmed out Ilpo's attribution.  Some hints at
https://subspace.kernel.org/etiquette.html

There should be a line like this:

  > On Tue, Aug 06, 2024 at 05:38:41PM +0300, Ilpo Järvinen wrote:
  ...
  > > These should be in numerical order.

so it's clear who wrote what.

> > On Tue, 6 Aug 2024, 412574090@163.com wrote:
> >
> > > From: weiyufeng <weiyufeng@kylinos.cn>
> > 
> > > PCIe r6.0, sec 7.7.7.1, defines a new 64.0 GT/s PCIe Extended Capability
> > > ID,Add the define for PCI_EXT_CAP_ID_PL_64GT for drivers that will want
> > > this whilst doing Gen6 accesses.
> > > 
> > > Signed-off-by: weiyufeng <weiyufeng@kylinos.cn>
> > > ---
> > >  include/uapi/linux/pci_regs.h | 1 +
> > >  1 file changed, 1 insertion(+)
> > > 
> > > diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
> > > index 94c00996e633..cc875534dae1 100644
> > > --- a/include/uapi/linux/pci_regs.h
> > > +++ b/include/uapi/linux/pci_regs.h
> > > @@ -741,6 +741,7 @@
> > >  #define PCI_EXT_CAP_ID_DLF	0x25	/* Data Link Feature */
> > >  #define PCI_EXT_CAP_ID_PL_16GT	0x26	/* Physical Layer 16.0 GT/s */
> > >  #define PCI_EXT_CAP_ID_PL_32GT  0x2A    /* Physical Layer 32.0 GT/s */
> > > +#define PCI_EXT_CAP_ID_PL_64GT  0x31    /* Physical Layer 64.0 GT/s */
> > >  #define PCI_EXT_CAP_ID_DOE	0x2E	/* Data Object Exchange */
> 
> > These should be in numerical order.
> In PCIe r6.0, PCI_EXT_CAP_ID_PL_64GT value is 0x31.

Right.  The #defines just need to be sorted in numerical order
(PCI_EXT_CAP_ID_PL_64GT would be last, after PCI_EXT_CAP_ID_DOE)
because PCI_EXT_CAP_ID_MAX is defined to be the one with the highest
numerical value, and it's hard to find that when they're not sorted.

> > >  #define PCI_EXT_CAP_ID_MAX	PCI_EXT_CAP_ID_DOE
> 
> > This was not adapted??
> PCIe r6.0, sec 7.7.7.1 have this definition。

I think Ilpo meant that if we add "#define PCI_EXT_CAP_ID_PL_64GT 0x31",
PCI_EXT_CAP_ID_MAX needs to be updated from PCI_EXT_CAP_ID_DOE to
PCI_EXT_CAP_ID_PL_64GT.

Bjorn

  reply	other threads:[~2024-08-08 17:22 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-08-06  2:27 [PATCH] PCI: Add PCI_EXT_CAP_ID_PL_64GT define 412574090
2024-08-06 14:38 ` Ilpo Järvinen
2024-08-08  2:32   ` 412574090
2024-08-08 17:22     ` Bjorn Helgaas [this message]
2024-08-06 17:59 ` Bjorn Helgaas
2024-08-08  2:12   ` 412574090
2024-08-08 16:20     ` Jonathan Cameron

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