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Fri, 16 Aug 2024 00:08:26 -0700 (PDT) Received: from thinkpad ([36.255.17.34]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2d3e3c74e33sm1058237a91.39.2024.08.16.00.08.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Aug 2024 00:08:25 -0700 (PDT) Date: Fri, 16 Aug 2024 12:38:19 +0530 From: Manivannan Sadhasivam To: Jim Quinlan Cc: linux-pci@vger.kernel.org, Nicolas Saenz Julienne , Bjorn Helgaas , Lorenzo Pieralisi , Cyril Brulebois , Stanimir Varbanov , Krzysztof Kozlowski , bcm-kernel-feedback-list@broadcom.com, jim2101024@gmail.com, Florian Fainelli , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Rob Herring , Philipp Zabel , "moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE" , "moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE" , open list Subject: Re: [PATCH v6 06/13] PCI: brcmstb: Use swinit reset if available Message-ID: <20240816070819.GK2331@thinkpad> References: <20240815225731.40276-1-james.quinlan@broadcom.com> <20240815225731.40276-7-james.quinlan@broadcom.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20240815225731.40276-7-james.quinlan@broadcom.com> On Thu, Aug 15, 2024 at 06:57:19PM -0400, Jim Quinlan wrote: > The 7712 SOC adds a software init reset device for the PCIe HW. > If found in the DT node, use it. > > Signed-off-by: Jim Quinlan Reviewed-by: Manivannan Sadhasivam - Mani > --- > drivers/pci/controller/pcie-brcmstb.c | 24 ++++++++++++++++++++++++ > 1 file changed, 24 insertions(+) > > diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c > index af14debd81d0..aa21c4c7b7f7 100644 > --- a/drivers/pci/controller/pcie-brcmstb.c > +++ b/drivers/pci/controller/pcie-brcmstb.c > @@ -266,6 +266,7 @@ struct brcm_pcie { > struct reset_control *rescal; > struct reset_control *perst_reset; > struct reset_control *bridge_reset; > + struct reset_control *swinit_reset; > int num_memc; > u64 memc_size[PCIE_BRCM_MAX_MEMC]; > u32 hw_rev; > @@ -1633,12 +1634,35 @@ static int brcm_pcie_probe(struct platform_device *pdev) > if (IS_ERR(pcie->bridge_reset)) > return PTR_ERR(pcie->bridge_reset); > > + pcie->swinit_reset = devm_reset_control_get_optional_exclusive(&pdev->dev, "swinit"); > + if (IS_ERR(pcie->swinit_reset)) > + return PTR_ERR(pcie->swinit_reset); > + > ret = clk_prepare_enable(pcie->clk); > if (ret) > return dev_err_probe(&pdev->dev, ret, "could not enable clock\n"); > > pcie->bridge_sw_init_set(pcie, 0); > > + if (pcie->swinit_reset) { > + ret = reset_control_assert(pcie->swinit_reset); > + if (ret) { > + clk_disable_unprepare(pcie->clk); > + return dev_err_probe(&pdev->dev, ret, > + "could not assert reset 'swinit'\n"); > + } > + > + /* HW team recommends 1us for proper sync and propagation of reset */ > + udelay(1); > + > + ret = reset_control_deassert(pcie->swinit_reset); > + if (ret) { > + clk_disable_unprepare(pcie->clk); > + return dev_err_probe(&pdev->dev, ret, > + "could not de-assert reset 'swinit'\n"); > + } > + } > + > ret = reset_control_reset(pcie->rescal); > if (ret) { > clk_disable_unprepare(pcie->clk); > -- > 2.17.1 > -- மணிவண்ணன் சதாசிவம்