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[209.17.68.221]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-717785b4db7sm114603b3a.207.2024.09.03.10.27.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Sep 2024 10:27:02 -0700 (PDT) Date: Wed, 4 Sep 2024 02:27:01 +0900 From: Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= To: Bjorn Helgaas Cc: Jim Quinlan , linux-pci@vger.kernel.org, Nicolas Saenz Julienne , Bjorn Helgaas , Lorenzo Pieralisi , Cyril Brulebois , Stanimir Varbanov , Manivannan Sadhasivam , Krzysztof Kozlowski , bcm-kernel-feedback-list@broadcom.com, jim2101024@gmail.com, Florian Fainelli , Lorenzo Pieralisi , Rob Herring , Philipp Zabel , "moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE" , "moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE" , open list Subject: Re: [PATCH v6 05/13] PCI: brcmstb: Use bridge reset if available Message-ID: <20240903172701.GA2873479@rocinante> References: <20240903144613.GC1403301@rocinante> <20240903171743.GA255170@bhelgaas> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20240903171743.GA255170@bhelgaas> Hello, [...] > > > > > static void brcm_pcie_bridge_sw_init_set_generic(struct brcm_pcie *pcie, u32 val) > > > > > { > > > > > - u32 tmp, mask = RGR1_SW_INIT_1_INIT_GENERIC_MASK; > > > > > - u32 shift = RGR1_SW_INIT_1_INIT_GENERIC_SHIFT; > > > > > + if (val) > > > > > + reset_control_assert(pcie->bridge_reset); > > > > > + else > > > > > + reset_control_deassert(pcie->bridge_reset); > > > > > > > > > > - tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); > > > > > - tmp = (tmp & ~mask) | ((val << shift) & mask); > > > > > - writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); > > > > > + if (!pcie->bridge_reset) { > > > > > + u32 tmp, mask = RGR1_SW_INIT_1_INIT_GENERIC_MASK; > > > > > + u32 shift = RGR1_SW_INIT_1_INIT_GENERIC_SHIFT; > > > > > + > > > > > + tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); > > > > > + tmp = (tmp & ~mask) | ((val << shift) & mask); > > > > > + writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); > > > > > + } > > > > > > > > This pattern looks goofy: > > > > > > > > reset_control_assert(pcie->bridge_reset); > > > > if (!pcie->bridge_reset) { > > > > ... > > > > > > > > If we're going to test pcie->bridge_reset at all, it should be first > > > > so it's obvious what's going on and the reader doesn't have to go > > > > verify that reset_control_assert() ignores and returns success for a > > > > NULL pointer: > > > > > > > > if (pcie->bridge_reset) { > > > > if (val) > > > > reset_control_assert(pcie->bridge_reset); > > > > else > > > > reset_control_deassert(pcie->bridge_reset); > > > > > > > > return; > > > > } > > > > > > > > u32 tmp, mask = RGR1_SW_INIT_1_INIT_GENERIC_MASK; > > > > ... > > > > > > > Will do. > > [...] > > > > You will do what? If you don't mind me asking. > > Can you just do the rework on the branch, Krzysztof? I think that > will be easier/quicker than having Jim repost the entire series. Will do. That was the idea, I believe. Krzysztof