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AJvYcCXezxPM6588Bdz0IIdA4oynchq5YBSGewKjWNSYUrkkCFoWMlqYJMkPE0gFkbJjnjVjPFQFhsLdYzg=@vger.kernel.org X-Gm-Message-State: AOJu0YxR3I+2Qq8O+jFJf+EronnkSc8+8ylUfBRauzI88wUjpcsDhO9+ eZNr3HTenIthpkZBwsCb2tuabTT/t4c2n6jHHAXm4+ye5sM8ZuqBa4uRPSzJyQ== X-Google-Smtp-Source: AGHT+IElFJh9mBN0d10CvX+yxAjA8cHTDsSZBmgENNb/EtffZEORF9F48GUK1FqLfVaqnR4xQfoX8Q== X-Received: by 2002:a17:902:ea0a:b0:205:3475:63be with SMTP id d9443c01a7336-206eeb8c61amr497735ad.25.1725557696776; Thu, 05 Sep 2024 10:34:56 -0700 (PDT) Received: from thinkpad ([120.60.52.248]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-206aea69770sm30809955ad.277.2024.09.05.10.34.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Sep 2024 10:34:56 -0700 (PDT) Date: Thu, 5 Sep 2024 23:04:37 +0530 From: Manivannan Sadhasivam To: Johan Hovold Cc: Richard Zhu , Lucas Stach , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Jingoo Han , Chuanhua Lei , Marek Vasut , Yoshihiro Shimoda , linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, imx@lists.linux.dev, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-arm-msm@vger.kernel.org, abel.vesa@linaro.org, johan+linaro@kernel.org, Shashank Babu Chinta Venkata Subject: Re: [PATCH v6 3/4] PCI: qcom: Add equalization settings for 16.0 GT/s Message-ID: <20240905173437.hm3hegv5zolaj7gj@thinkpad> References: <20240904-pci-qcom-gen4-stability-v6-0-ec39f7ae3f62@linaro.org> <20240904-pci-qcom-gen4-stability-v6-3-ec39f7ae3f62@linaro.org> <20240905152742.4llkcjvvu3klmo6j@thinkpad> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: On Thu, Sep 05, 2024 at 06:27:36PM +0200, Johan Hovold wrote: > On Thu, Sep 05, 2024 at 08:57:42PM +0530, Manivannan Sadhasivam wrote: > > On Wed, Sep 04, 2024 at 11:39:09AM +0200, Johan Hovold wrote: > > > > > diff --git a/drivers/pci/controller/dwc/pcie-qcom-common.h b/drivers/pci/controller/dwc/pcie-qcom-common.h > > > > new file mode 100644 > > > > index 000000000000..259e04b7bdf9 > > > > --- /dev/null > > > > +++ b/drivers/pci/controller/dwc/pcie-qcom-common.h > > > > @@ -0,0 +1,8 @@ > > > > +/* SPDX-License-Identifier: GPL-2.0 */ > > > > +/* > > > > + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. > > > > + */ > > > > + > > > > +#include "pcie-designware.h" > > > > > > You only need a forward declaration: > > > > > > struct dw_pcie; > > > > > > > + > > > > +void qcom_pcie_common_set_16gt_eq_settings(struct dw_pcie *pci); > > > > > > Compile guard still missing. > > Sorry, I meant to say *include* guard here. > Okay. I got confused initially. > > Perhaps we can just get rid of the Kconfig entry and build it by default for > > both RC and EP drivers? I don't see a value in building it as a separate module. > > And we may also move more common code in the future. > > It is already built by default for both drivers. I'm not sure what > you're suggesting here. > Right now it is selected by both drivers using a Kconfig symbol. But I'm thinking of building it by default as below: -obj-$(CONFIG_PCIE_QCOM) += pcie-qcom.o -obj-$(CONFIG_PCIE_QCOM_EP) += pcie-qcom-ep.o +obj-$(CONFIG_PCIE_QCOM) += pcie-qcom.o pcie-qcom-common.o +obj-$(CONFIG_PCIE_QCOM_EP) += pcie-qcom-ep.o pcie-qcom-common.o A separate Kconfig symbol is not really needed here as this file contains common code required by both the drivers. - Mani -- மணிவண்ணன் சதாசிவம்