Re: [PATCH 2/2] PCI: xilinx-cpm: Add support for Versal CPM5 Root Port controller-1

Krzysztof Kozlowski
2024-09-06T09:56:31Z

On 06/09/2024 11:31, Thippeswamy Havalige wrote:
> In the CPM5, controller-1 has platform-specific error interrupt bits
> located at different offsets compared to controller-0.
>
> Signed-off-by: Thippeswamy Havalige <thippesw@amd.com>
> ---
> drivers/pci/controller/pcie-xilinx-cpm.c | 39 +++++++++++++++++++-----
> 1 file changed, 32 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/pci/controller/pcie-xilinx-cpm.c b/drivers/pci/controller/pcie-xilinx-cpm.c
> index a0f5e1d67b04..d672f620bc4c 100644
> --- a/drivers/pci/controller/pcie-xilinx-cpm.c
> +++ b/drivers/pci/controller/pcie-xilinx-cpm.c
> @@ -30,10 +30,13 @@
> #define XILINX_CPM_PCIE_REG_IDRN_MASK 0x00000E3C
> #define XILINX_CPM_PCIE_MISC_IR_STATUS 0x00000340
> #define XILINX_CPM_PCIE_MISC_IR_ENABLE 0x00000348
> -#define XILINX_CPM_PCIE_MISC_IR_LOCAL BIT(1)
> +#define XILINX_CPM_PCIE0_MISC_IR_LOCAL BIT(1)
> +#define XILINX_CPM_PCIE1_MISC_IR_LOCAL BIT(2)
>
> -#define XILINX_CPM_PCIE_IR_STATUS 0x000002A0
> -#define XILINX_CPM_PCIE_IR_ENABLE 0x000002A8
> +#define XILINX_CPM_PCIE0_IR_STATUS 0x000002A0
> +#define XILINX_CPM_PCIE1_IR_STATUS 0x000002B4
> +#define XILINX_CPM_PCIE0_IR_ENABLE 0x000002A8
> +#define XILINX_CPM_PCIE1_IR_ENABLE 0x000002BC
> #define XILINX_CPM_PCIE_IR_LOCAL BIT(0)
>
> #define IMR(x) BIT(XILINX_PCIE_INTR_ ##x)
> @@ -280,10 +283,17 @@ static void xilinx_cpm_pcie_event_flow(struct irq_desc *desc)
> pcie_write(port, val, XILINX_CPM_PCIE_REG_IDR);
>
> if (port->variant->version == CPM5) {
> - val = readl_relaxed(port->cpm_base + XILINX_CPM_PCIE_IR_STATUS);
> + val = readl_relaxed(port->cpm_base + XILINX_CPM_PCIE0_IR_STATUS);
> if (val)
> writel_relaxed(val, port->cpm_base +
> - XILINX_CPM_PCIE_IR_STATUS);
> + XILINX_CPM_PCIE0_IR_STATUS);
> + }
> +

There are no blank lines allowed between arms of conditional statements.
Please follow coding style. This case is explained there.

Best regards,
Krzysztof