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[209.17.68.221]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7db49910131sm171000a12.38.2024.09.13.15.48.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Sep 2024 15:48:18 -0700 (PDT) Date: Sat, 14 Sep 2024 07:48:17 +0900 From: Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= To: Manivannan Sadhasivam Cc: lpieralisi@kernel.org, bhelgaas@google.com, robh@kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Dmitry Baryshkov Subject: Re: [PATCH v3] PCI: qcom-ep: Enable controller resources like PHY only after refclk is available Message-ID: <20240913224817.GA635227@rocinante> References: <20240830082319.51387-1-manivannan.sadhasivam@linaro.org> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20240830082319.51387-1-manivannan.sadhasivam@linaro.org> Hello, > qcom_pcie_enable_resources() is called by qcom_pcie_ep_probe() and it > enables the controller resources like clocks, regulator, PHY. On one of the > new unreleased Qcom SoC, PHY enablement depends on the active refclk. And > on all of the supported Qcom endpoint SoCs, refclk comes from the host > (RC). So calling qcom_pcie_enable_resources() without refclk causes the > NoC (Network On Chip) error in the endpoint SoC and in turn results in a > whole SoC crash and rebooting into EDL (Emergency Download) mode which is > an unrecoverable state. > > But qcom_pcie_enable_resources() is already called by > qcom_pcie_perst_deassert() when PERST# is deasserted, and refclk is > available at that time. > > Hence, remove the unnecessary call to qcom_pcie_enable_resources() from > qcom_pcie_ep_probe() to prevent the above mentioned crash. > > It should be noted that this commit prevents the crash only under normal > working condition (booting endpoint before host), but the crash may also > occur if PERST# assert happens at the wrong time. For avoiding the crash > completely, it is recommended to use SRIS mode which allows the endpoint > SoC to generate its own refclk. The driver is not supporting SRIS mode > currently, but will be added in the future. Applied to controller/qcom, thank you! [1/1] PCI: qcom-ep: Enable controller resources like PHY only after refclk is available https://git.kernel.org/pci/pci/c/d3745e3ae6c0 Krzysztof