From: Frank Li <Frank.Li@nxp.com>
To: "Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Krzysztof Wilczyński" <kw@linux.com>,
"Manivannan Sadhasivam" <manivannan.sadhasivam@linaro.org>,
"Rob Herring" <robh@kernel.org>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
"Conor Dooley" <conor+dt@kernel.org>,
"Abraham I" <kishon@kernel.org>,
"Saravana Kannan" <saravanak@google.com>,
"Jingoo Han" <jingoohan1@gmail.com>,
"Gustavo Pimentel" <gustavo.pimentel@synopsys.com>,
"Jesper Nilsson" <jesper.nilsson@axis.com>,
"Richard Zhu" <hongxing.zhu@nxp.com>,
"Lucas Stach" <l.stach@pengutronix.de>,
"Shawn Guo" <shawnguo@kernel.org>,
"Sascha Hauer" <s.hauer@pengutronix.de>,
"Pengutronix Kernel Team" <kernel@pengutronix.de>,
"Fabio Estevam" <festevam@gmail.com>
Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-arm-kernel@axis.com,
linux-arm-kernel@lists.infradead.org, imx@lists.linux.dev,
"Krzysztof Wilczyński" <kwilczynski@kernel.org>,
"Frank Li" <Frank.Li@nxp.com>
Subject: [PATCH 3/9] of: address: Add device type pci-ep
Date: Thu, 19 Sep 2024 18:03:03 -0400 [thread overview]
Message-ID: <20240919-pcie_ep_range-v1-3-b3e9d62780b7@nxp.com> (raw)
In-Reply-To: <20240919-pcie_ep_range-v1-0-b3e9d62780b7@nxp.com>
The PCI bus device tree supports 'ranges' properties that indicate how to
convert PCI addresses to CPU addresses. Many PCI controllers are dual-role
controllers, supporting both Root Complex (RC) and Endpoint (EP) modes. The
EP side also needs similar information for proper address translation.
Add device type 'pci-ep' and use the same PCI address parser function to
parser PCI EP's ranges property.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
drivers/of/address.c | 24 +++++++++++++++++++++---
1 file changed, 21 insertions(+), 3 deletions(-)
diff --git a/drivers/of/address.c b/drivers/of/address.c
index d886f16df8a6e..c98e212d53dc1 100644
--- a/drivers/of/address.c
+++ b/drivers/of/address.c
@@ -117,13 +117,13 @@ static int of_bus_default_flags_translate(__be32 *addr, u64 offset, int na)
return of_bus_default_translate(addr + 1, offset, na - 1);
}
-#ifdef CONFIG_PCI
+#if defined(CONFIG_PCI) || defined(CONFIG_PCI_ENDPOINT)
static unsigned int of_bus_pci_get_flags(const __be32 *addr)
{
unsigned int flags = 0;
u32 w = be32_to_cpup(addr);
- if (!IS_ENABLED(CONFIG_PCI))
+ if (!IS_ENABLED(CONFIG_PCI) && !IS_ENABLED(CONFIG_PCI_ENDPOINT))
return 0;
switch((w >> 24) & 0x03) {
@@ -172,6 +172,11 @@ static int of_bus_pci_match(struct device_node *np)
of_node_is_pcie(np, "pcie");
}
+static int of_bus_pci_ep_match(struct device_node *np)
+{
+ return of_node_is_type(np, "pci-ep") || of_node_is_pcie(np, "pcie-ep");
+}
+
static void of_bus_pci_count_cells(struct device_node *np,
int *addrc, int *sizec)
{
@@ -196,7 +201,7 @@ static u64 of_bus_pci_map(__be32 *addr, const __be32 *range, int na, int ns,
return of_bus_default_map(addr, range, na, ns, pna, fna);
}
-#endif /* CONFIG_PCI */
+#endif /* CONFIG_PCI || CONFIG_PCI_ENDPOINT */
static int __of_address_resource_bounds(struct resource *r, u64 start, u64 size)
{
@@ -354,6 +359,19 @@ static struct of_bus of_busses[] = {
.get_flags = of_bus_pci_get_flags,
},
#endif /* CONFIG_PCI */
+#ifdef CONFIG_PCI_ENDPOINT
+ /* PCI Endpoint */
+ {
+ .name = "pci-ep",
+ .addresses = "assigned-addresses",
+ .match = of_bus_pci_ep_match,
+ .count_cells = of_bus_pci_count_cells,
+ .map = of_bus_pci_map,
+ .translate = of_bus_default_flags_translate,
+ .flag_cells = 1,
+ .get_flags = of_bus_pci_get_flags,
+ },
+#endif /* CONFIG_PCI_EP */
/* ISA */
{
.name = "isa",
--
2.34.1
next prev parent reply other threads:[~2024-09-19 22:03 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-09-19 22:03 [PATCH 0/9] PCI-EP: Add 'ranges' support for PCI endpoint devices Frank Li
2024-09-19 22:03 ` [PATCH 1/9] dt-bindings: PCI: pci-ep: Document 'ranges' property Frank Li
2024-09-19 22:03 ` [PATCH 2/9] of: address: Add argument 'name' for of_node_is_pcie() Frank Li
2024-09-19 22:03 ` Frank Li [this message]
2024-09-19 22:03 ` [PATCH 4/9] dt-bindings: PCI: snps,dw-pcie-ep: 'addr_space' not required if 'ranges' present Frank Li
2024-09-19 22:03 ` [PATCH 5/9] PCI: dwc: ep: Replace phys_base and addr_size with range Frank Li
2024-09-19 22:03 ` [PATCH 6/9] PCI: dwc: ep: Use 'ranges' from DT if 'addr_space' is missing Frank Li
2024-09-19 22:03 ` [PATCH 7/9] dt-bindings: PCI: fsl,imx6q-pcie-ep: Add compatible string fsl,imx8q-pcie-ep Frank Li
2024-09-19 22:03 ` [PATCH 8/9] PCI: imx6: Pass correct sub mode when calling phy_set_mode_ext() Frank Li
2024-09-19 22:03 ` [PATCH 9/9] PCI: imx6: Add i.MX8Q PCIe Endpoint (EP) support Frank Li
2024-09-21 14:43 ` [PATCH 0/9] PCI-EP: Add 'ranges' support for PCI endpoint devices Rob Herring
2024-09-21 19:18 ` Frank Li
2024-09-23 16:14 ` Frank Li
2024-09-23 19:02 ` Frank Li
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