[PATCH 0/9] PCI-EP: Add 'ranges' support for PCI endpoint devices

[PATCH 0/9] PCI-EP: Add 'ranges' support for PCI endpoint devices

[Frank Li]

The PCI bus device tree supports 'ranges' properties that indicate
how to convert PCI addresses to CPU addresses. Many PCI controllers
are dual-role controllers, supporting both Root Complex (RC) and
Endpoint (EP) modes. The EP side also needs similar information for
proper address translation.

This commit introduces several changes to add 'ranges' support for
PCI endpoint devices:

1. **Modify of_address.c**: Add support for the new `device_type`
   "pci-ep", enabling it to parse 'ranges' using the same functions
   as for PCI devices.

2. **Update DesignWare PCIe EP driver**: Enhance the driver to
   support 'ranges' when 'addr_space' is missing, maintaining
   compatibility with existing drivers.

3. **Update binding documentation**: Modify the device tree bindings
   to include 'ranges' support and make 'addr_space' an optional
   entry in 'reg-names'.

4. **Add i.MX8QXP EP support**: Incorporate support for the
   i.MX8QXP PCIe EP in the driver.

i.MX8QXP PCIe dts is upstreaming.  Below is pcie-ep part.

pcieb_ep: pcie-ep@5f010000 {
                compatible = "fsl,imx8q-pcie-ep";
                reg = <0x5f010000 0x00010000>;
                reg-names = "dbi";
                #address-cells = <3>;
                #size-cells = <2>;
                device_type = "pci-ep";
                ranges = <0x82000000 0 0x80000000 0x70000000 0 0x10000000>;
                num-lanes = <1>;
                interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
                interrupt-names = "dma";
                clocks = <&pcieb_lpcg IMX_LPCG_CLK_6>,
                         <&pcieb_lpcg IMX_LPCG_CLK_4>,
                         <&pcieb_lpcg IMX_LPCG_CLK_5>;
                clock-names = "dbi", "mstr", "slv";
                power-domains = <&pd IMX_SC_R_PCIE_B>;
                fsl,max-link-speed = <3>;
                num-ib-windows = <6>;
                num-ob-windows = <6>;
                status = "disabled";
};

These changes improve PCIe EP support by allowing proper address
translation using 'ranges', ensuring compatibility with devices that
rely on this information.

Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
Frank Li (9):
      dt-bindings: PCI: pci-ep: Document 'ranges' property
      of: address: Add argument 'name' for of_node_is_pcie()
      of: address: Add device type pci-ep
      dt-bindings: PCI: snps,dw-pcie-ep: 'addr_space' not required if 'ranges' present
      PCI: dwc: ep: Replace phys_base and addr_size with range
      PCI: dwc: ep: Use 'ranges' from DT if 'addr_space' is missing
      dt-bindings: PCI: fsl,imx6q-pcie-ep: Add compatible string fsl,imx8q-pcie-ep
      PCI: imx6: Pass correct sub mode when calling phy_set_mode_ext()
      PCI: imx6: Add i.MX8Q PCIe Endpoint (EP) support

 .../devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml | 42 +++++++++++++++++++++-
 Documentation/devicetree/bindings/pci/pci-ep.yaml  | 30 ++++++++++++++++
 .../bindings/pci/snps,dw-pcie-common.yaml          |  4 +--
 .../devicetree/bindings/pci/snps,dw-pcie-ep.yaml   | 21 ++++++++---
 drivers/of/address.c                               | 30 ++++++++++++----
 drivers/pci/controller/dwc/pci-imx6.c              | 24 ++++++++++++-
 drivers/pci/controller/dwc/pcie-artpec6.c          |  2 +-
 drivers/pci/controller/dwc/pcie-designware-ep.c    | 23 ++++++++----
 drivers/pci/controller/dwc/pcie-designware.h       |  4 +--
 9 files changed, 157 insertions(+), 23 deletions(-)
---
base-commit: 909eac36208b70a22fd0d1c3097e3af98dca7599
change-id: 20240918-pcie_ep_range-4c5c5e300e19

Best regards,
---
Frank Li <Frank.Li@nxp.com>

[PATCH 1/9] dt-bindings: PCI: pci-ep: Document 'ranges' property

[Frank Li]

The PCI bus device tree supports 'ranges' properties that indicate how to
convert PCI addresses to CPU addresses. Many PCI controllers are dual-role
controllers, supporting both Root Complex (RC) and Endpoint (EP) modes. The
EP side also needs similar information for proper address translation.

Add 'ranges' property for pcie-ep, which format is same as PCI's ranges.

Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
 Documentation/devicetree/bindings/pci/pci-ep.yaml | 30 +++++++++++++++++++++++
 1 file changed, 30 insertions(+)

diff --git a/Documentation/devicetree/bindings/pci/pci-ep.yaml b/Documentation/devicetree/bindings/pci/pci-ep.yaml
index f75000e3093db..2de00d2bf7326 100644
--- a/Documentation/devicetree/bindings/pci/pci-ep.yaml
+++ b/Documentation/devicetree/bindings/pci/pci-ep.yaml
@@ -17,6 +17,26 @@ properties:
   $nodename:
     pattern: "^pcie-ep@"
 
+  ranges:
+    description:
+      Outbound memory regions, which is extend reg 'addr_space' if pci bus
+      address is not equal cpu address or there are more one outbound
+      memory regions.
+    oneOf:
+      - type: boolean
+      - minItems: 1
+        maxItems: 32    # Should be enough
+        items:
+          minItems: 5
+          maxItems: 8
+          additionalItems: true
+          items:
+            - enum:
+                - 0x42000000
+                - 0x43000000
+                - 0x82000000
+                - 0x83000000
+
   max-functions:
     description: Maximum number of functions that can be configured
     $ref: /schemas/types.yaml#/definitions/uint8
@@ -42,6 +62,16 @@ properties:
     default: 1
     maximum: 16
 
+  device_type:
+    $ref: /schemas/types.yaml#/definitions/string
+    const: pci-ep
+
+  "#address-cells":
+    const: 3
+
+  "#size-cells":
+    const: 2
+
   linux,pci-domain:
     description:
       If present this property assigns a fixed PCI domain number to a PCI

-- 
2.34.1

[PATCH 2/9] of: address: Add argument 'name' for of_node_is_pcie()

[Frank Li]

Add argument 'name' for help function of_node_is_pcie(). Prepare for adding
pci-ep support.

Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
 drivers/of/address.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/of/address.c b/drivers/of/address.c
index 286f0c161e332..d886f16df8a6e 100644
--- a/drivers/of/address.c
+++ b/drivers/of/address.c
@@ -147,9 +147,9 @@ static unsigned int of_bus_pci_get_flags(const __be32 *addr)
  * PCI bus specific translator
  */
 
-static bool of_node_is_pcie(struct device_node *np)
+static bool of_node_is_pcie(struct device_node *np, const char *name)
 {
-	bool is_pcie = of_node_name_eq(np, "pcie");
+	bool is_pcie = of_node_name_eq(np, name);
 
 	if (is_pcie)
 		pr_warn_once("%pOF: Missing device_type\n", np);
@@ -169,7 +169,7 @@ static int of_bus_pci_match(struct device_node *np)
 	 */
 	return of_node_is_type(np, "pci") || of_node_is_type(np, "pciex") ||
 		of_node_is_type(np, "vci") || of_node_is_type(np, "ht") ||
-		of_node_is_pcie(np);
+		of_node_is_pcie(np, "pcie");
 }
 
 static void of_bus_pci_count_cells(struct device_node *np,

-- 
2.34.1

[PATCH 3/9] of: address: Add device type pci-ep

[Frank Li]

The PCI bus device tree supports 'ranges' properties that indicate how to
convert PCI addresses to CPU addresses. Many PCI controllers are dual-role
controllers, supporting both Root Complex (RC) and Endpoint (EP) modes. The
EP side also needs similar information for proper address translation.

Add device type 'pci-ep' and use the same PCI address parser function to
parser PCI EP's ranges property.

Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
 drivers/of/address.c | 24 +++++++++++++++++++++---
 1 file changed, 21 insertions(+), 3 deletions(-)

diff --git a/drivers/of/address.c b/drivers/of/address.c
index d886f16df8a6e..c98e212d53dc1 100644
--- a/drivers/of/address.c
+++ b/drivers/of/address.c
@@ -117,13 +117,13 @@ static int of_bus_default_flags_translate(__be32 *addr, u64 offset, int na)
 	return of_bus_default_translate(addr + 1, offset, na - 1);
 }
 
-#ifdef CONFIG_PCI
+#if defined(CONFIG_PCI) || defined(CONFIG_PCI_ENDPOINT)
 static unsigned int of_bus_pci_get_flags(const __be32 *addr)
 {
 	unsigned int flags = 0;
 	u32 w = be32_to_cpup(addr);
 
-	if (!IS_ENABLED(CONFIG_PCI))
+	if (!IS_ENABLED(CONFIG_PCI) && !IS_ENABLED(CONFIG_PCI_ENDPOINT))
 		return 0;
 
 	switch((w >> 24) & 0x03) {
@@ -172,6 +172,11 @@ static int of_bus_pci_match(struct device_node *np)
 		of_node_is_pcie(np, "pcie");
 }
 
+static int of_bus_pci_ep_match(struct device_node *np)
+{
+	return of_node_is_type(np, "pci-ep") || of_node_is_pcie(np, "pcie-ep");
+}
+
 static void of_bus_pci_count_cells(struct device_node *np,
 				   int *addrc, int *sizec)
 {
@@ -196,7 +201,7 @@ static u64 of_bus_pci_map(__be32 *addr, const __be32 *range, int na, int ns,
 	return of_bus_default_map(addr, range, na, ns, pna, fna);
 }
 
-#endif /* CONFIG_PCI */
+#endif /* CONFIG_PCI || CONFIG_PCI_ENDPOINT */
 
 static int __of_address_resource_bounds(struct resource *r, u64 start, u64 size)
 {
@@ -354,6 +359,19 @@ static struct of_bus of_busses[] = {
 		.get_flags = of_bus_pci_get_flags,
 	},
 #endif /* CONFIG_PCI */
+#ifdef CONFIG_PCI_ENDPOINT
+	/* PCI Endpoint */
+	{
+		.name = "pci-ep",
+		.addresses = "assigned-addresses",
+		.match = of_bus_pci_ep_match,
+		.count_cells = of_bus_pci_count_cells,
+		.map = of_bus_pci_map,
+		.translate = of_bus_default_flags_translate,
+		.flag_cells = 1,
+		.get_flags = of_bus_pci_get_flags,
+	},
+#endif /* CONFIG_PCI_EP */
 	/* ISA */
 	{
 		.name = "isa",

-- 
2.34.1

[PATCH 4/9] dt-bindings: PCI: snps,dw-pcie-ep: 'addr_space' not required if 'ranges' present

[Frank Li]

Do not require 'addr_space' in 'reg-names' when the device uses the
'ranges' property to indicate the outbound address space. This maintains
the same restriction for cases where 'ranges' is absent.

minItems of 'reg' and 'reg-names' change to 1 because only one 'dbi'
register space is required if use 'ranges' describe outbound memory space.

minItems of 'reg' and 'reg-names' in snps,dw-pcie-common.yaml also change
to 1 from 2. It doesn't loss restriction because it is 2 in
snps,dw-pcie.yaml.

Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
 .../bindings/pci/snps,dw-pcie-common.yaml           |  4 ++--
 .../devicetree/bindings/pci/snps,dw-pcie-ep.yaml    | 21 +++++++++++++++++----
 2 files changed, 19 insertions(+), 6 deletions(-)

diff --git a/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml b/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml
index dc05761c5cf93..16d5fe77d117a 100644
--- a/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml
+++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml
@@ -32,11 +32,11 @@ properties:
       is selected. Note the PCIe CFG-space, PL and Shadow registers are
       specific for each activated function, while the rest of the sub-spaces
       are common for all of them (if there are more than one).
-    minItems: 2
+    minItems: 1
     maxItems: 7
 
   reg-names:
-    minItems: 2
+    minItems: 1
     maxItems: 7
 
   interrupts:
diff --git a/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml
index f474b9e3fc7e2..184c519d2b7c6 100644
--- a/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml
+++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml
@@ -25,18 +25,33 @@ select:
 allOf:
   - $ref: /schemas/pci/pci-ep.yaml#
   - $ref: /schemas/pci/snps,dw-pcie-common.yaml#
+  - if:
+      not:
+        required:
+          - ranges
+    then:
+      properties:
+        reg:
+          minItems: 2
+        reg-names:
+          minItems: 2
+          allOf:
+            - contains:
+                const: addr_space
 
 properties:
+  ranges: true
+
   reg:
     description:
       DBI, DBI2 reg-spaces and outbound memory window are required for the
       normal controller functioning. iATU memory IO region is also required
       if the space is unrolled (IP-core version >= 4.80a).
-    minItems: 2
+    minItems: 1
     maxItems: 7
 
   reg-names:
-    minItems: 2
+    minItems: 1
     maxItems: 7
     items:
       oneOf:
@@ -106,8 +121,6 @@ properties:
     allOf:
       - contains:
           const: dbi
-      - contains:
-          const: addr_space
 
   interrupts:
     description:

-- 
2.34.1

[PATCH 5/9] PCI: dwc: ep: Replace phys_base and addr_size with range

[Frank Li]

The CPU address and PCI address are the same in most system. But in some
systems such as i.MX8QXP, they are different. Previously, we used the
cpu_addr_fixup() hook function to handle address translation. However, the
device tree can use the common 'ranges' property to indicate how CPU and
PCI addresses are translated.

Replace the fields 'phys_base' and 'addr_size' in struct dw_pcie_ep with
struct of_pci_range 'range'. The of_pci_range already includes cpu_addr
and size information. Prepare to add 'ranges' support.

Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
 drivers/pci/controller/dwc/pcie-artpec6.c       | 2 +-
 drivers/pci/controller/dwc/pcie-designware-ep.c | 6 +++---
 drivers/pci/controller/dwc/pcie-designware.h    | 4 ++--
 3 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/pci/controller/dwc/pcie-artpec6.c b/drivers/pci/controller/dwc/pcie-artpec6.c
index f8e7283dacd47..f93d3c7a980c8 100644
--- a/drivers/pci/controller/dwc/pcie-artpec6.c
+++ b/drivers/pci/controller/dwc/pcie-artpec6.c
@@ -104,7 +104,7 @@ static u64 artpec6_pcie_cpu_addr_fixup(struct dw_pcie *pci, u64 cpu_addr)
 	case DW_PCIE_RC_TYPE:
 		return cpu_addr - pp->cfg0_base;
 	case DW_PCIE_EP_TYPE:
-		return cpu_addr - ep->phys_base;
+		return cpu_addr - ep->range.cpu_addr;
 	default:
 		dev_err(pci->dev, "UNKNOWN device type\n");
 	}
diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
index 43ba5c6738df1..feac1a435f764 100644
--- a/drivers/pci/controller/dwc/pcie-designware-ep.c
+++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
@@ -872,8 +872,8 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
 	if (!res)
 		return -EINVAL;
 
-	ep->phys_base = res->start;
-	ep->addr_size = resource_size(res);
+	ep->range.cpu_addr = ep->range.pci_addr = res->start;
+	ep->range.size = resource_size(res);
 
 	if (ep->ops->pre_init)
 		ep->ops->pre_init(ep);
@@ -891,7 +891,7 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
 	if (ret < 0)
 		epc->max_functions = 1;
 
-	ret = pci_epc_mem_init(epc, ep->phys_base, ep->addr_size,
+	ret = pci_epc_mem_init(epc, ep->range.cpu_addr, ep->range.size,
 			       ep->page_size);
 	if (ret < 0) {
 		dev_err(dev, "Failed to initialize address space\n");
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index 347ab74ac35aa..59109a32b2afc 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -19,6 +19,7 @@
 #include <linux/gpio/consumer.h>
 #include <linux/irq.h>
 #include <linux/msi.h>
+#include <linux/of_address.h>
 #include <linux/pci.h>
 #include <linux/reset.h>
 
@@ -409,8 +410,7 @@ struct dw_pcie_ep {
 	struct pci_epc		*epc;
 	struct list_head	func_list;
 	const struct dw_pcie_ep_ops *ops;
-	phys_addr_t		phys_base;
-	size_t			addr_size;
+	struct of_pci_range	range;
 	size_t			page_size;
 	u8			bar_to_atu[PCI_STD_NUM_BARS];
 	phys_addr_t		*outbound_addr;

-- 
2.34.1

[PATCH 6/9] PCI: dwc: ep: Use 'ranges' from DT if 'addr_space' is missing

[Frank Li]

Some systems (such as i.MX8QXP) have different CPU and PCI addresses,
requiring address translation. If 'addr_space' is missing, retrieve the
address translation information from the 'ranges' property in the device
tree. This allows support for systems where CPU and PCI addresses differ
without relying solely on 'addr_space'.

Update the driver to use 'ranges' from the device tree when 'addr_space' is
not provided, keeping compatibility with existed systems.

Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
 drivers/pci/controller/dwc/pcie-designware-ep.c | 21 ++++++++++++++++-----
 1 file changed, 16 insertions(+), 5 deletions(-)

diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
index feac1a435f764..1b013d2fe694a 100644
--- a/drivers/pci/controller/dwc/pcie-designware-ep.c
+++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
@@ -294,7 +294,7 @@ static int dw_pcie_ep_map_addr(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
 
 	atu.func_no = func_no;
 	atu.type = PCIE_ATU_TYPE_MEM;
-	atu.cpu_addr = addr;
+	atu.cpu_addr = addr + ep->range.bus_addr - ep->range.cpu_addr;
 	atu.pci_addr = pci_addr;
 	atu.size = size;
 	ret = dw_pcie_ep_outbound_atu(ep, &atu);
@@ -861,6 +861,7 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
 	struct device *dev = pci->dev;
 	struct platform_device *pdev = to_platform_device(dev);
 	struct device_node *np = dev->of_node;
+	struct of_pci_range_parser parser;
 
 	INIT_LIST_HEAD(&ep->func_list);
 
@@ -869,11 +870,21 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
 		return ret;
 
 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "addr_space");
-	if (!res)
-		return -EINVAL;
+	if (!res) {
+		ret = of_pci_range_parser_init(&parser, np);
+		if (ret)
+			return ret;
+
+		for_each_of_pci_range(&parser, &ep->range)
+			if ((ep->range.flags & IORESOURCE_TYPE_BITS) == IORESOURCE_MEM)
+				break;
 
-	ep->range.cpu_addr = ep->range.pci_addr = res->start;
-	ep->range.size = resource_size(res);
+		if (!ep->range.size)
+			return -EINVAL;
+	} else {
+		ep->range.cpu_addr = ep->range.bus_addr = res->start;
+		ep->range.size = resource_size(res);
+	}
 
 	if (ep->ops->pre_init)
 		ep->ops->pre_init(ep);

-- 
2.34.1

[PATCH 7/9] dt-bindings: PCI: fsl,imx6q-pcie-ep: Add compatible string fsl,imx8q-pcie-ep

[Frank Li]

Add new compatible string fsl,imx8q-pcie-ep for iMX8Q. Mark 'ranges'
property as required because CPU address is difference PCI address.

Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
 .../devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml | 42 +++++++++++++++++++++-
 1 file changed, 41 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml
index 84ca12e8b25be..6f6eb1dfff40a 100644
--- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml
+++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml
@@ -22,6 +22,7 @@ properties:
       - fsl,imx8mm-pcie-ep
       - fsl,imx8mq-pcie-ep
       - fsl,imx8mp-pcie-ep
+      - fsl,imx8q-pcie-ep
       - fsl,imx95-pcie-ep
 
   clocks:
@@ -45,6 +46,9 @@ properties:
     items:
       - const: dma
 
+  ranges:
+    maxItems: 1
+
 required:
   - compatible
   - reg
@@ -74,6 +78,21 @@ allOf:
             - const: dbi2
             - const: atu
 
+  - if:
+      properties:
+        compatible:
+          enum:
+            - fsl,imx8q-pcie-ep
+    then:
+      properties:
+        reg:
+          maxItems: 1
+        reg-names:
+          items:
+            - const: dbi
+      required:
+        - ranges
+
   - if:
       properties:
         compatible:
@@ -109,7 +128,14 @@ allOf:
             - const: pcie_bus
             - const: pcie_phy
             - const: pcie_aux
-    else:
+
+  - if:
+      properties:
+        compatible:
+          enum:
+            - fsl,imx8mm-pcie-ep
+            - fsl,imx8mp-pcie-ep
+    then:
       properties:
         clocks:
           maxItems: 3
@@ -119,6 +145,20 @@ allOf:
             - const: pcie_bus
             - const: pcie_aux
 
+  - if:
+      properties:
+        compatible:
+          enum:
+            - fsl,imxq-pcie-ep
+    then:
+      properties:
+        clocks:
+          maxItems: 3
+        clock-names:
+          items:
+            - const: dbi
+            - const: mstr
+            - const: slv
 
 unevaluatedProperties: false
 

-- 
2.34.1

[PATCH 8/9] PCI: imx6: Pass correct sub mode when calling phy_set_mode_ext()

[Frank Li]

Fix hardcoding to Root Complex (RC) mode by adding a drvdata mode check.
Pass PHY_MODE_PCIE_EP if the PCI controller operates in Endpoint (EP) mode.

Fixes: 8026f2d8e8a9 ("PCI: imx6: Call common PHY API to set mode, speed, and submode")
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
 drivers/pci/controller/dwc/pci-imx6.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index 808d1f1054173..bdc2b372e6c13 100644
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -961,7 +961,9 @@ static int imx_pcie_host_init(struct dw_pcie_rp *pp)
 			goto err_clk_disable;
 		}
 
-		ret = phy_set_mode_ext(imx_pcie->phy, PHY_MODE_PCIE, PHY_MODE_PCIE_RC);
+		ret = phy_set_mode_ext(imx_pcie->phy, PHY_MODE_PCIE,
+				       imx_pcie->drvdata->mode == DW_PCIE_EP_TYPE ?
+						PHY_MODE_PCIE_EP : PHY_MODE_PCIE_RC);
 		if (ret) {
 			dev_err(dev, "unable to set PCIe PHY mode\n");
 			goto err_phy_exit;

-- 
2.34.1

[PATCH 9/9] PCI: imx6: Add i.MX8Q PCIe Endpoint (EP) support

[Frank Li]

Add support for i.MX8Q series (i.MX8QM, i.MX8QXP, and i.MX8DXL) PCIe
Endpoint (EP). On i.MX8Q platforms, the PCI bus addresses differ from the
CPU addresses. The DesignWare (DWC) driver already handles this in the
common code by using the 'ranges' property in the Device Tree (DT) file.

Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
 drivers/pci/controller/dwc/pci-imx6.c | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index bdc2b372e6c13..1e58c24137e7f 100644
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -70,6 +70,7 @@ enum imx_pcie_variants {
 	IMX8MQ_EP,
 	IMX8MM_EP,
 	IMX8MP_EP,
+	IMX8Q_EP,
 	IMX95_EP,
 };
 
@@ -1079,6 +1080,16 @@ static const struct pci_epc_features imx8m_pcie_epc_features = {
 	.align = SZ_64K,
 };
 
+static const struct pci_epc_features imx8q_pcie_epc_features = {
+	.linkup_notifier = false,
+	.msi_capable = true,
+	.msix_capable = false,
+	.bar[BAR_1] = { .type = BAR_RESERVED, },
+	.bar[BAR_3] = { .type = BAR_RESERVED, },
+	.bar[BAR_5] = { .type = BAR_RESERVED, },
+	.align = SZ_64K,
+};
+
 /*
  * BAR#	| Default BAR enable	| Default BAR Type	| Default BAR Size	| BAR Sizing Scheme
  * ================================================================================================
@@ -1645,6 +1656,14 @@ static const struct imx_pcie_drvdata drvdata[] = {
 		.epc_features = &imx8m_pcie_epc_features,
 		.enable_ref_clk = imx8mm_pcie_enable_ref_clk,
 	},
+	[IMX8Q_EP] = {
+		.variant = IMX8Q_EP,
+		.flags = IMX_PCIE_FLAG_HAS_PHYDRV,
+		.mode = DW_PCIE_EP_TYPE,
+		.epc_features = &imx8q_pcie_epc_features,
+		.clk_names = imx8q_clks,
+		.clks_cnt = ARRAY_SIZE(imx8q_clks),
+	},
 	[IMX95_EP] = {
 		.variant = IMX95_EP,
 		.flags = IMX_PCIE_FLAG_HAS_SERDES |
@@ -1674,6 +1693,7 @@ static const struct of_device_id imx_pcie_of_match[] = {
 	{ .compatible = "fsl,imx8mq-pcie-ep", .data = &drvdata[IMX8MQ_EP], },
 	{ .compatible = "fsl,imx8mm-pcie-ep", .data = &drvdata[IMX8MM_EP], },
 	{ .compatible = "fsl,imx8mp-pcie-ep", .data = &drvdata[IMX8MP_EP], },
+	{ .compatible = "fsl,imx8q-pcie-ep", .data = &drvdata[IMX8Q_EP], },
 	{ .compatible = "fsl,imx95-pcie-ep", .data = &drvdata[IMX95_EP], },
 	{},
 };

-- 
2.34.1

Re: [PATCH 0/9] PCI-EP: Add 'ranges' support for PCI endpoint devices

[Rob Herring]

On Thu, Sep 19, 2024 at 5:03 PM Frank Li <Frank.Li@nxp.com> wrote:
>
> The PCI bus device tree supports 'ranges' properties that indicate
> how to convert PCI addresses to CPU addresses. Many PCI controllers
> are dual-role controllers, supporting both Root Complex (RC) and
> Endpoint (EP) modes. The EP side also needs similar information for
> proper address translation.
>
> This commit introduces several changes to add 'ranges' support for
> PCI endpoint devices:
>
> 1. **Modify of_address.c**: Add support for the new `device_type`
>    "pci-ep", enabling it to parse 'ranges' using the same functions
>    as for PCI devices.
>
> 2. **Update DesignWare PCIe EP driver**: Enhance the driver to
>    support 'ranges' when 'addr_space' is missing, maintaining
>    compatibility with existing drivers.
>
> 3. **Update binding documentation**: Modify the device tree bindings
>    to include 'ranges' support and make 'addr_space' an optional
>    entry in 'reg-names'.
>
> 4. **Add i.MX8QXP EP support**: Incorporate support for the
>    i.MX8QXP PCIe EP in the driver.
>
> i.MX8QXP PCIe dts is upstreaming.  Below is pcie-ep part.
>
> pcieb_ep: pcie-ep@5f010000 {
>                 compatible = "fsl,imx8q-pcie-ep";
>                 reg = <0x5f010000 0x00010000>;
>                 reg-names = "dbi";
>                 #address-cells = <3>;
>                 #size-cells = <2>;
>                 device_type = "pci-ep";
>                 ranges = <0x82000000 0 0x80000000 0x70000000 0 0x10000000>;

How does a PCI endpoint set PCI addresses? Those get assigned by the
PCI host system. They can't be static in DT.

If you need the PCI address, just read your BAR registers.

In general, why do you need this when none of the other PCI endpoint
drivers have needed this?

Rob

Re: [PATCH 0/9] PCI-EP: Add 'ranges' support for PCI endpoint devices

[Frank Li]

On Sat, Sep 21, 2024 at 09:43:17AM -0500, Rob Herring wrote:
> On Thu, Sep 19, 2024 at 5:03 PM Frank Li <Frank.Li@nxp.com> wrote:
> >
> > The PCI bus device tree supports 'ranges' properties that indicate
> > how to convert PCI addresses to CPU addresses. Many PCI controllers
> > are dual-role controllers, supporting both Root Complex (RC) and
> > Endpoint (EP) modes. The EP side also needs similar information for
> > proper address translation.
> >
> > This commit introduces several changes to add 'ranges' support for
> > PCI endpoint devices:
> >
> > 1. **Modify of_address.c**: Add support for the new `device_type`
> >    "pci-ep", enabling it to parse 'ranges' using the same functions
> >    as for PCI devices.
> >
> > 2. **Update DesignWare PCIe EP driver**: Enhance the driver to
> >    support 'ranges' when 'addr_space' is missing, maintaining
> >    compatibility with existing drivers.
> >
> > 3. **Update binding documentation**: Modify the device tree bindings
> >    to include 'ranges' support and make 'addr_space' an optional
> >    entry in 'reg-names'.
> >
> > 4. **Add i.MX8QXP EP support**: Incorporate support for the
> >    i.MX8QXP PCIe EP in the driver.
> >
> > i.MX8QXP PCIe dts is upstreaming.  Below is pcie-ep part.
> >
> > pcieb_ep: pcie-ep@5f010000 {
> >                 compatible = "fsl,imx8q-pcie-ep";
> >                 reg = <0x5f010000 0x00010000>;
> >                 reg-names = "dbi";
> >                 #address-cells = <3>;
> >                 #size-cells = <2>;
> >                 device_type = "pci-ep";
> >                 ranges = <0x82000000 0 0x80000000 0x70000000 0 0x10000000>;
>
> How does a PCI endpoint set PCI addresses? Those get assigned by the
> PCI host system. They can't be static in DT.

PCI address is set by other channel, such as RC write some place in bar0.

It indicates EP side outbound windows mapping. See below detail.


                                  Endpoint          Root complex
                                 ┌───────┐        ┌─────────┐
                   ┌─────┐       │ EP    │        │         │      ┌─────┐
                   │     │       │ Ctrl  │        │         │      │ CPU │
                   │ DDR │       │       │        │ ┌────┐  │      └──┬──┘
                   │     │◄──────┼─ATU ◄─┼────────┼─┤BarN│◄─┼─────────┘
                   │     │       │       │        │ └────┘  │ Outbound Transfer
                   └─────┘       │       │        │         │
                                 │       │        │         │
                                 │       │        │         │
                                 │       │        │         │ Inbound Transfer
                                 │       │        │         │      ┌──▼──┐
                  ┌───────┐      │       │        │ ┌───────┼─────►│DDR  │
                  │       │ outbound Transfer*    │ │       │      └─────┘
       ┌─────┐    │ Bus   ┼─────►│ ATU  ─┬────────┼─┘       │
       │     │    │ Fabric│Bus   │       │ PCI Addr         │
       │ CPU ├───►│       │Addr  │       │ 0xA000_0000      │
       │     │CPU │       │0x8000_0000   │        │         │
       └─────┘Addr└───────┘      │       │        │         │
              0x7000_0000        └───────┘        └─────────┘


This ranges descript above diagram Endpoint outbound Transfer*'s
information. There are address space (previous use addr_space in reg-name)
indicate such informaiton, such as [0x7000_00000, 0xB000_0000] as PCI EP
outbound windows. when cpu write 0x7000_0000, data will write to EP ctrl,
the ATU in EP ctrl convert to PCI address such 0xA000,0000, then write
to RC's DDR>

The PCI Addr 0xA000_0000 information was sent to EP driver by use other
channel, such as RC write it some place in Bar0.

The 'range' here indicated EP side's outbound windows information. Most
system CPU address is the same as bus address. but in imx8q, it is
difference. Bus fabric convert 0x7000_0000 to 0x8000_00000.

So need range indicate such address convertion.

>
> If you need the PCI address, just read your BAR registers.
>
> In general, why do you need this when none of the other PCI endpoint
> drivers have needed this?

Most system, the address is the same. Some system convert is simple, just
cut some high address bit, so their driver hardcode it. Maybe imx8QM have
first one, they have more than one controller and address map is not
such simple.

We use customer dt property in downstream kernel, but I think common
solution should be better, other drivers can remove their hardcode in
future. And it will be more symmetry with PCI host side's property.

Frank
>
> Rob

Re: [PATCH 0/9] PCI-EP: Add 'ranges' support for PCI endpoint devices

[Frank Li]

On Sat, Sep 21, 2024 at 03:18:50PM -0400, Frank Li wrote:
> On Sat, Sep 21, 2024 at 09:43:17AM -0500, Rob Herring wrote:
> > On Thu, Sep 19, 2024 at 5:03 PM Frank Li <Frank.Li@nxp.com> wrote:
> > >
> > > The PCI bus device tree supports 'ranges' properties that indicate
> > > how to convert PCI addresses to CPU addresses. Many PCI controllers
> > > are dual-role controllers, supporting both Root Complex (RC) and
> > > Endpoint (EP) modes. The EP side also needs similar information for
> > > proper address translation.
> > >
> > > This commit introduces several changes to add 'ranges' support for
> > > PCI endpoint devices:
> > >
> > > 1. **Modify of_address.c**: Add support for the new `device_type`
> > >    "pci-ep", enabling it to parse 'ranges' using the same functions
> > >    as for PCI devices.
> > >
> > > 2. **Update DesignWare PCIe EP driver**: Enhance the driver to
> > >    support 'ranges' when 'addr_space' is missing, maintaining
> > >    compatibility with existing drivers.
> > >
> > > 3. **Update binding documentation**: Modify the device tree bindings
> > >    to include 'ranges' support and make 'addr_space' an optional
> > >    entry in 'reg-names'.
> > >
> > > 4. **Add i.MX8QXP EP support**: Incorporate support for the
> > >    i.MX8QXP PCIe EP in the driver.
> > >
> > > i.MX8QXP PCIe dts is upstreaming.  Below is pcie-ep part.
> > >
> > > pcieb_ep: pcie-ep@5f010000 {
> > >                 compatible = "fsl,imx8q-pcie-ep";
> > >                 reg = <0x5f010000 0x00010000>;
> > >                 reg-names = "dbi";
> > >                 #address-cells = <3>;
> > >                 #size-cells = <2>;
> > >                 device_type = "pci-ep";
> > >                 ranges = <0x82000000 0 0x80000000 0x70000000 0 0x10000000>;
> >
> > How does a PCI endpoint set PCI addresses? Those get assigned by the
> > PCI host system. They can't be static in DT.
>
> PCI address is set by other channel, such as RC write some place in bar0.
>
> It indicates EP side outbound windows mapping. See below detail.
>
>
>                                   Endpoint          Root complex
>                                  ┌───────┐        ┌─────────┐
>                    ┌─────┐       │ EP    │        │         │      ┌─────┐
>                    │     │       │ Ctrl  │        │         │      │ CPU │
>                    │ DDR │       │       │        │ ┌────┐  │      └──┬──┘
>                    │     │◄──────┼─ATU ◄─┼────────┼─┤BarN│◄─┼─────────┘
>                    │     │       │       │        │ └────┘  │ Outbound Transfer
>                    └─────┘       │       │        │         │
>                                  │       │        │         │
>                                  │       │        │         │
>                                  │       │        │         │ Inbound Transfer
>                                  │       │        │         │      ┌──▼──┐
>                   ┌───────┐      │       │        │ ┌───────┼─────►│DDR  │
>                   │       │ outbound Transfer*    │ │       │      └─────┘
>        ┌─────┐    │ Bus   ┼─────►│ ATU  ─┬────────┼─┘       │
>        │     │    │ Fabric│Bus   │       │ PCI Addr         │
>        │ CPU ├───►│       │Addr  │       │ 0xA000_0000      │
>        │     │CPU │       │0x8000_0000   │        │         │
>        └─────┘Addr└───────┘      │       │        │         │
>               0x7000_0000        └───────┘        └─────────┘
>
>
> This ranges descript above diagram Endpoint outbound Transfer*'s
> information. There are address space (previous use addr_space in reg-name)
> indicate such informaiton, such as [0x7000_00000, 0xB000_0000] as PCI EP
> outbound windows. when cpu write 0x7000_0000, data will write to EP ctrl,
> the ATU in EP ctrl convert to PCI address such 0xA000,0000, then write
> to RC's DDR>
>
> The PCI Addr 0xA000_0000 information was sent to EP driver by use other
> channel, such as RC write it some place in Bar0.
>
> The 'range' here indicated EP side's outbound windows information. Most
> system CPU address is the same as bus address. but in imx8q, it is
> difference. Bus fabric convert 0x7000_0000 to 0x8000_00000.
>
> So need range indicate such address convertion.
>
> >
> > If you need the PCI address, just read your BAR registers.
> >
> > In general, why do you need this when none of the other PCI endpoint
> > drivers have needed this?
>
> Most system, the address is the same. Some system convert is simple, just
> cut some high address bit, so their driver hardcode it. Maybe imx8QM have
> first one, they have more than one controller and address map is not
> such simple.
>
> We use customer dt property in downstream kernel, but I think common
> solution should be better, other drivers can remove their hardcode in
> future. And it will be more symmetry with PCI host side's property.

I found a more simple the method, will post v2 soon.

Frank

>
> Frank
> >
> > Rob

Re: [PATCH 0/9] PCI-EP: Add 'ranges' support for PCI endpoint devices

[Frank Li]

On Mon, Sep 23, 2024 at 12:14:27PM -0400, Frank Li wrote:
> On Sat, Sep 21, 2024 at 03:18:50PM -0400, Frank Li wrote:
> > On Sat, Sep 21, 2024 at 09:43:17AM -0500, Rob Herring wrote:
> > > On Thu, Sep 19, 2024 at 5:03 PM Frank Li <Frank.Li@nxp.com> wrote:
> > > >
> > > > The PCI bus device tree supports 'ranges' properties that indicate
> > > > how to convert PCI addresses to CPU addresses. Many PCI controllers
> > > > are dual-role controllers, supporting both Root Complex (RC) and
> > > > Endpoint (EP) modes. The EP side also needs similar information for
> > > > proper address translation.
> > > >
> > > > This commit introduces several changes to add 'ranges' support for
> > > > PCI endpoint devices:
> > > >
> > > > 1. **Modify of_address.c**: Add support for the new `device_type`
> > > >    "pci-ep", enabling it to parse 'ranges' using the same functions
> > > >    as for PCI devices.
> > > >
> > > > 2. **Update DesignWare PCIe EP driver**: Enhance the driver to
> > > >    support 'ranges' when 'addr_space' is missing, maintaining
> > > >    compatibility with existing drivers.
> > > >
> > > > 3. **Update binding documentation**: Modify the device tree bindings
> > > >    to include 'ranges' support and make 'addr_space' an optional
> > > >    entry in 'reg-names'.
> > > >
> > > > 4. **Add i.MX8QXP EP support**: Incorporate support for the
> > > >    i.MX8QXP PCIe EP in the driver.
> > > >
> > > > i.MX8QXP PCIe dts is upstreaming.  Below is pcie-ep part.
> > > >
> > > > pcieb_ep: pcie-ep@5f010000 {
> > > >                 compatible = "fsl,imx8q-pcie-ep";
> > > >                 reg = <0x5f010000 0x00010000>;
> > > >                 reg-names = "dbi";
> > > >                 #address-cells = <3>;
> > > >                 #size-cells = <2>;
> > > >                 device_type = "pci-ep";
> > > >                 ranges = <0x82000000 0 0x80000000 0x70000000 0 0x10000000>;
> > >
> > > How does a PCI endpoint set PCI addresses? Those get assigned by the
> > > PCI host system. They can't be static in DT.
> >
> > PCI address is set by other channel, such as RC write some place in bar0.
> >
> > It indicates EP side outbound windows mapping. See below detail.
> >
> >
> >                                   Endpoint          Root complex
> >                                  ┌───────┐        ┌─────────┐
> >                    ┌─────┐       │ EP    │        │         │      ┌─────┐
> >                    │     │       │ Ctrl  │        │         │      │ CPU │
> >                    │ DDR │       │       │        │ ┌────┐  │      └──┬──┘
> >                    │     │◄──────┼─ATU ◄─┼────────┼─┤BarN│◄─┼─────────┘
> >                    │     │       │       │        │ └────┘  │ Outbound Transfer
> >                    └─────┘       │       │        │         │
> >                                  │       │        │         │
> >                                  │       │        │         │
> >                                  │       │        │         │ Inbound Transfer
> >                                  │       │        │         │      ┌──▼──┐
> >                   ┌───────┐      │       │        │ ┌───────┼─────►│DDR  │
> >                   │       │ outbound Transfer*    │ │       │      └─────┘
> >        ┌─────┐    │ Bus   ┼─────►│ ATU  ─┬────────┼─┘       │
> >        │     │    │ Fabric│Bus   │       │ PCI Addr         │
> >        │ CPU ├───►│       │Addr  │       │ 0xA000_0000      │
> >        │     │CPU │       │0x8000_0000   │        │         │
> >        └─────┘Addr└───────┘      │       │        │         │
> >               0x7000_0000        └───────┘        └─────────┘
> >
> >
> > This ranges descript above diagram Endpoint outbound Transfer*'s
> > information. There are address space (previous use addr_space in reg-name)
> > indicate such informaiton, such as [0x7000_00000, 0xB000_0000] as PCI EP
> > outbound windows. when cpu write 0x7000_0000, data will write to EP ctrl,
> > the ATU in EP ctrl convert to PCI address such 0xA000,0000, then write
> > to RC's DDR>
> >
> > The PCI Addr 0xA000_0000 information was sent to EP driver by use other
> > channel, such as RC write it some place in Bar0.
> >
> > The 'range' here indicated EP side's outbound windows information. Most
> > system CPU address is the same as bus address. but in imx8q, it is
> > difference. Bus fabric convert 0x7000_0000 to 0x8000_00000.
> >
> > So need range indicate such address convertion.
> >
> > >
> > > If you need the PCI address, just read your BAR registers.
> > >
> > > In general, why do you need this when none of the other PCI endpoint
> > > drivers have needed this?
> >
> > Most system, the address is the same. Some system convert is simple, just
> > cut some high address bit, so their driver hardcode it. Maybe imx8QM have
> > first one, they have more than one controller and address map is not
> > such simple.
> >
> > We use customer dt property in downstream kernel, but I think common
> > solution should be better, other drivers can remove their hardcode in
> > future. And it will be more symmetry with PCI host side's property.
>
> I found a more simple the method, will post v2 soon.

V2 post at https://lore.kernel.org/imx/20240923-pcie_ep_range-v2-0-78d2ea434d9f@nxp.com/T/#t
, which more simple and reasonable.

Frank

>
> Frank
>
> >
> > Frank
> > >
> > > Rob