From: Frank Li <Frank.Li@nxp.com>
To: "Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Krzysztof Wilczyński" <kw@linux.com>,
"Manivannan Sadhasivam" <manivannan.sadhasivam@linaro.org>,
"Rob Herring" <robh@kernel.org>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
"Conor Dooley" <conor+dt@kernel.org>,
"Abraham I" <kishon@kernel.org>,
"Saravana Kannan" <saravanak@google.com>,
"Jingoo Han" <jingoohan1@gmail.com>,
"Gustavo Pimentel" <gustavo.pimentel@synopsys.com>,
"Jesper Nilsson" <jesper.nilsson@axis.com>,
"Richard Zhu" <hongxing.zhu@nxp.com>,
"Lucas Stach" <l.stach@pengutronix.de>,
"Shawn Guo" <shawnguo@kernel.org>,
"Sascha Hauer" <s.hauer@pengutronix.de>,
"Pengutronix Kernel Team" <kernel@pengutronix.de>,
"Fabio Estevam" <festevam@gmail.com>
Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-arm-kernel@axis.com,
linux-arm-kernel@lists.infradead.org, imx@lists.linux.dev,
"Krzysztof Wilczyński" <kwilczynski@kernel.org>,
"Frank Li" <Frank.Li@nxp.com>
Subject: [PATCH 9/9] PCI: imx6: Add i.MX8Q PCIe Endpoint (EP) support
Date: Thu, 19 Sep 2024 18:03:09 -0400 [thread overview]
Message-ID: <20240919-pcie_ep_range-v1-9-b3e9d62780b7@nxp.com> (raw)
In-Reply-To: <20240919-pcie_ep_range-v1-0-b3e9d62780b7@nxp.com>
Add support for i.MX8Q series (i.MX8QM, i.MX8QXP, and i.MX8DXL) PCIe
Endpoint (EP). On i.MX8Q platforms, the PCI bus addresses differ from the
CPU addresses. The DesignWare (DWC) driver already handles this in the
common code by using the 'ranges' property in the Device Tree (DT) file.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
drivers/pci/controller/dwc/pci-imx6.c | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index bdc2b372e6c13..1e58c24137e7f 100644
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -70,6 +70,7 @@ enum imx_pcie_variants {
IMX8MQ_EP,
IMX8MM_EP,
IMX8MP_EP,
+ IMX8Q_EP,
IMX95_EP,
};
@@ -1079,6 +1080,16 @@ static const struct pci_epc_features imx8m_pcie_epc_features = {
.align = SZ_64K,
};
+static const struct pci_epc_features imx8q_pcie_epc_features = {
+ .linkup_notifier = false,
+ .msi_capable = true,
+ .msix_capable = false,
+ .bar[BAR_1] = { .type = BAR_RESERVED, },
+ .bar[BAR_3] = { .type = BAR_RESERVED, },
+ .bar[BAR_5] = { .type = BAR_RESERVED, },
+ .align = SZ_64K,
+};
+
/*
* BAR# | Default BAR enable | Default BAR Type | Default BAR Size | BAR Sizing Scheme
* ================================================================================================
@@ -1645,6 +1656,14 @@ static const struct imx_pcie_drvdata drvdata[] = {
.epc_features = &imx8m_pcie_epc_features,
.enable_ref_clk = imx8mm_pcie_enable_ref_clk,
},
+ [IMX8Q_EP] = {
+ .variant = IMX8Q_EP,
+ .flags = IMX_PCIE_FLAG_HAS_PHYDRV,
+ .mode = DW_PCIE_EP_TYPE,
+ .epc_features = &imx8q_pcie_epc_features,
+ .clk_names = imx8q_clks,
+ .clks_cnt = ARRAY_SIZE(imx8q_clks),
+ },
[IMX95_EP] = {
.variant = IMX95_EP,
.flags = IMX_PCIE_FLAG_HAS_SERDES |
@@ -1674,6 +1693,7 @@ static const struct of_device_id imx_pcie_of_match[] = {
{ .compatible = "fsl,imx8mq-pcie-ep", .data = &drvdata[IMX8MQ_EP], },
{ .compatible = "fsl,imx8mm-pcie-ep", .data = &drvdata[IMX8MM_EP], },
{ .compatible = "fsl,imx8mp-pcie-ep", .data = &drvdata[IMX8MP_EP], },
+ { .compatible = "fsl,imx8q-pcie-ep", .data = &drvdata[IMX8Q_EP], },
{ .compatible = "fsl,imx95-pcie-ep", .data = &drvdata[IMX95_EP], },
{},
};
--
2.34.1
next prev parent reply other threads:[~2024-09-19 22:04 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-09-19 22:03 [PATCH 0/9] PCI-EP: Add 'ranges' support for PCI endpoint devices Frank Li
2024-09-19 22:03 ` [PATCH 1/9] dt-bindings: PCI: pci-ep: Document 'ranges' property Frank Li
2024-09-19 22:03 ` [PATCH 2/9] of: address: Add argument 'name' for of_node_is_pcie() Frank Li
2024-09-19 22:03 ` [PATCH 3/9] of: address: Add device type pci-ep Frank Li
2024-09-19 22:03 ` [PATCH 4/9] dt-bindings: PCI: snps,dw-pcie-ep: 'addr_space' not required if 'ranges' present Frank Li
2024-09-19 22:03 ` [PATCH 5/9] PCI: dwc: ep: Replace phys_base and addr_size with range Frank Li
2024-09-19 22:03 ` [PATCH 6/9] PCI: dwc: ep: Use 'ranges' from DT if 'addr_space' is missing Frank Li
2024-09-19 22:03 ` [PATCH 7/9] dt-bindings: PCI: fsl,imx6q-pcie-ep: Add compatible string fsl,imx8q-pcie-ep Frank Li
2024-09-19 22:03 ` [PATCH 8/9] PCI: imx6: Pass correct sub mode when calling phy_set_mode_ext() Frank Li
2024-09-19 22:03 ` Frank Li [this message]
2024-09-21 14:43 ` [PATCH 0/9] PCI-EP: Add 'ranges' support for PCI endpoint devices Rob Herring
2024-09-21 19:18 ` Frank Li
2024-09-23 16:14 ` Frank Li
2024-09-23 19:02 ` Frank Li
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