* [PATCH v2 1/4] PCI: dwc: ep: Add bus_addr_base for outbound window
2024-09-23 18:59 [PATCH v2 0/4] PCI: ep: dwc/imx6: Add bus address support for PCI endpoint devices Frank Li
@ 2024-09-23 18:59 ` Frank Li
2024-10-16 18:08 ` Manivannan Sadhasivam
2024-09-23 18:59 ` [PATCH v2 2/4] dt-bindings: PCI: fsl,imx6q-pcie-ep: Add compatible string fsl,imx8q-pcie-ep Frank Li
` (3 subsequent siblings)
4 siblings, 1 reply; 14+ messages in thread
From: Frank Li @ 2024-09-23 18:59 UTC (permalink / raw)
To: Lorenzo Pieralisi, Krzysztof Wilczyński,
Manivannan Sadhasivam, Rob Herring, Bjorn Helgaas,
Krzysztof Kozlowski, Conor Dooley, Abraham I, Saravana Kannan,
Jingoo Han, Gustavo Pimentel, Jesper Nilsson, Richard Zhu,
Lucas Stach, Shawn Guo, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam
Cc: linux-pci, devicetree, linux-kernel, linux-arm-kernel,
linux-arm-kernel, imx, Krzysztof Wilczyński, Frank Li
Endpoint Root complex
┌───────┐ ┌─────────┐
┌─────┐ │ EP │ │ │ ┌─────┐
│ │ │ Ctrl │ │ │ │ CPU │
│ DDR │ │ │ │ ┌────┐ │ └──┬──┘
│ │◄──────┼─ATU ◄─┼────────┼─┤BarN│◄─┼─────────┘
│ │ │ │ │ └────┘ │ Outbound Transfer
└─────┘ │ │ │ │
│ │ │ │
│ │ │ │
│ │ │ │ Inbound Transfer
│ │ │ │ ┌──▼──┐
┌───────┐ │ │ │ ┌───────┼─────►│DDR │
│ │ outbound Transfer* │ │ │ └─────┘
┌─────┐ │ Bus ┼─────►│ ATU ─┬────────┼─┘ │
│ │ │ Fabric│Bus │ │ PCI Addr │
│ CPU ├───►│ │Addr │ │ 0xA000_0000 │
│ │CPU │ │0x8000_0000 │ │ │
└─────┘Addr└───────┘ │ │ │ │
0x7000_0000 └───────┘ └─────────┘
Add `bus_addr_base` to configure the outbound window address for CPU write.
The bus fabric generally passes the same address to the PCIe EP controller,
but some bus fabrics convert the address before sending it to the PCIe EP
controller.
Above diagram, CPU write data to outbound windows address 0x7000_0000,
Bus fabric convert it to 0x8000_0000. ATU should use bus address
0x8000_0000 as input address and convert to PCI address 0xA000_0000.
Previously, `cpu_addr_fixup()` was used to handle address conversion. Now,
the device tree provides this information, preferring a common method.
bus@5f000000 {
compatible = "simple-bus";
ranges = <0x5f000000 0x0 0x5f000000 0x21000000>,
<0x80000000 0x0 0x70000000 0x10000000>;
pcie-ep@5f010000 {
reg = <0x5f010000 0x00010000>,
<0x80000000 0x10000000>;
reg-names = "dbi", "addr_space";
...
};
...
};
'ranges' in bus@5f000000 descript how address convert from CPU address
to bus address.
Use `of_property_read_reg()` to obtain the bus address and set it to the
ATU correctly, eliminating the need for vendor-specific cpu_addr_fixup().
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
drivers/pci/controller/dwc/pcie-designware-ep.c | 12 +++++++++++-
drivers/pci/controller/dwc/pcie-designware.h | 1 +
2 files changed, 12 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
index 43ba5c6738df1..51eefdcb1b293 100644
--- a/drivers/pci/controller/dwc/pcie-designware-ep.c
+++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
@@ -9,6 +9,7 @@
#include <linux/align.h>
#include <linux/bitfield.h>
#include <linux/of.h>
+#include <linux/of_address.h>
#include <linux/platform_device.h>
#include "pcie-designware.h"
@@ -294,7 +295,7 @@ static int dw_pcie_ep_map_addr(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
atu.func_no = func_no;
atu.type = PCIE_ATU_TYPE_MEM;
- atu.cpu_addr = addr;
+ atu.cpu_addr = addr - ep->phys_base + ep->bus_addr_base;
atu.pci_addr = pci_addr;
atu.size = size;
ret = dw_pcie_ep_outbound_atu(ep, &atu);
@@ -861,6 +862,7 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
struct device *dev = pci->dev;
struct platform_device *pdev = to_platform_device(dev);
struct device_node *np = dev->of_node;
+ int index;
INIT_LIST_HEAD(&ep->func_list);
@@ -873,6 +875,14 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
return -EINVAL;
ep->phys_base = res->start;
+ ep->bus_addr_base = ep->phys_base;
+
+ index = of_property_match_string(np, "reg-names", "addr_space");
+ if (index < 0)
+ return -EINVAL;
+
+ of_property_read_reg(np, index, &ep->bus_addr_base, NULL);
+
ep->addr_size = resource_size(res);
if (ep->ops->pre_init)
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index 347ab74ac35aa..c189781524fb8 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -410,6 +410,7 @@ struct dw_pcie_ep {
struct list_head func_list;
const struct dw_pcie_ep_ops *ops;
phys_addr_t phys_base;
+ phys_addr_t bus_addr_base;
size_t addr_size;
size_t page_size;
u8 bar_to_atu[PCI_STD_NUM_BARS];
--
2.34.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH v2 1/4] PCI: dwc: ep: Add bus_addr_base for outbound window
2024-09-23 18:59 ` [PATCH v2 1/4] PCI: dwc: ep: Add bus_addr_base for outbound window Frank Li
@ 2024-10-16 18:08 ` Manivannan Sadhasivam
2024-10-16 19:10 ` Frank Li
0 siblings, 1 reply; 14+ messages in thread
From: Manivannan Sadhasivam @ 2024-10-16 18:08 UTC (permalink / raw)
To: Frank Li
Cc: Lorenzo Pieralisi, Krzysztof Wilczyński, Rob Herring,
Bjorn Helgaas, Krzysztof Kozlowski, Conor Dooley, Abraham I,
Saravana Kannan, Jingoo Han, Gustavo Pimentel, Jesper Nilsson,
Richard Zhu, Lucas Stach, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, linux-pci, devicetree,
linux-kernel, linux-arm-kernel, linux-arm-kernel, imx,
Krzysztof Wilczyński
On Mon, Sep 23, 2024 at 02:59:19PM -0400, Frank Li wrote:
> Endpoint Root complex
> ┌───────┐ ┌─────────┐
> ┌─────┐ │ EP │ │ │ ┌─────┐
> │ │ │ Ctrl │ │ │ │ CPU │
> │ DDR │ │ │ │ ┌────┐ │ └──┬──┘
> │ │◄──────┼─ATU ◄─┼────────┼─┤BarN│◄─┼─────────┘
> │ │ │ │ │ └────┘ │ Outbound Transfer
> └─────┘ │ │ │ │
> │ │ │ │
> │ │ │ │
> │ │ │ │ Inbound Transfer
> │ │ │ │ ┌──▼──┐
> ┌───────┐ │ │ │ ┌───────┼─────►│DDR │
> │ │ outbound Transfer* │ │ │ └─────┘
> ┌─────┐ │ Bus ┼─────►│ ATU ─┬────────┼─┘ │
> │ │ │ Fabric│Bus │ │ PCI Addr │
> │ CPU ├───►│ │Addr │ │ 0xA000_0000 │
> │ │CPU │ │0x8000_0000 │ │ │
> └─────┘Addr└───────┘ │ │ │ │
> 0x7000_0000 └───────┘ └─────────┘
>
> Add `bus_addr_base` to configure the outbound window address for CPU write.
> The bus fabric generally passes the same address to the PCIe EP controller,
> but some bus fabrics convert the address before sending it to the PCIe EP
> controller.
>
> Above diagram, CPU write data to outbound windows address 0x7000_0000,
> Bus fabric convert it to 0x8000_0000. ATU should use bus address
> 0x8000_0000 as input address and convert to PCI address 0xA000_0000.
>
> Previously, `cpu_addr_fixup()` was used to handle address conversion. Now,
> the device tree provides this information, preferring a common method.
>
> bus@5f000000 {
> compatible = "simple-bus";
> ranges = <0x5f000000 0x0 0x5f000000 0x21000000>,
> <0x80000000 0x0 0x70000000 0x10000000>;
>
> pcie-ep@5f010000 {
> reg = <0x5f010000 0x00010000>,
> <0x80000000 0x10000000>;
> reg-names = "dbi", "addr_space";
> ...
> };
> ...
> };
>
> 'ranges' in bus@5f000000 descript how address convert from CPU address
> to bus address.
>
> Use `of_property_read_reg()` to obtain the bus address and set it to the
> ATU correctly, eliminating the need for vendor-specific cpu_addr_fixup().
>
> Signed-off-by: Frank Li <Frank.Li@nxp.com>
> ---
> drivers/pci/controller/dwc/pcie-designware-ep.c | 12 +++++++++++-
> drivers/pci/controller/dwc/pcie-designware.h | 1 +
> 2 files changed, 12 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
> index 43ba5c6738df1..51eefdcb1b293 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-ep.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
> @@ -9,6 +9,7 @@
> #include <linux/align.h>
> #include <linux/bitfield.h>
> #include <linux/of.h>
> +#include <linux/of_address.h>
> #include <linux/platform_device.h>
>
> #include "pcie-designware.h"
> @@ -294,7 +295,7 @@ static int dw_pcie_ep_map_addr(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
>
> atu.func_no = func_no;
> atu.type = PCIE_ATU_TYPE_MEM;
> - atu.cpu_addr = addr;
> + atu.cpu_addr = addr - ep->phys_base + ep->bus_addr_base;
If you convert the address here, aren't he drivers with cpu_addr_fixup() will be
broken? You should only update the address if the callback is not available.
- Mani
> atu.pci_addr = pci_addr;
> atu.size = size;
> ret = dw_pcie_ep_outbound_atu(ep, &atu);
> @@ -861,6 +862,7 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
> struct device *dev = pci->dev;
> struct platform_device *pdev = to_platform_device(dev);
> struct device_node *np = dev->of_node;
> + int index;
>
> INIT_LIST_HEAD(&ep->func_list);
>
> @@ -873,6 +875,14 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
> return -EINVAL;
>
> ep->phys_base = res->start;
> + ep->bus_addr_base = ep->phys_base;
> +
> + index = of_property_match_string(np, "reg-names", "addr_space");
> + if (index < 0)
> + return -EINVAL;
> +
> + of_property_read_reg(np, index, &ep->bus_addr_base, NULL);
> +
> ep->addr_size = resource_size(res);
>
> if (ep->ops->pre_init)
> diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
> index 347ab74ac35aa..c189781524fb8 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.h
> +++ b/drivers/pci/controller/dwc/pcie-designware.h
> @@ -410,6 +410,7 @@ struct dw_pcie_ep {
> struct list_head func_list;
> const struct dw_pcie_ep_ops *ops;
> phys_addr_t phys_base;
> + phys_addr_t bus_addr_base;
> size_t addr_size;
> size_t page_size;
> u8 bar_to_atu[PCI_STD_NUM_BARS];
>
> --
> 2.34.1
>
--
மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [PATCH v2 1/4] PCI: dwc: ep: Add bus_addr_base for outbound window
2024-10-16 18:08 ` Manivannan Sadhasivam
@ 2024-10-16 19:10 ` Frank Li
0 siblings, 0 replies; 14+ messages in thread
From: Frank Li @ 2024-10-16 19:10 UTC (permalink / raw)
To: Manivannan Sadhasivam
Cc: Lorenzo Pieralisi, Krzysztof Wilczyński, Rob Herring,
Bjorn Helgaas, Krzysztof Kozlowski, Conor Dooley, Abraham I,
Saravana Kannan, Jingoo Han, Gustavo Pimentel, Jesper Nilsson,
Richard Zhu, Lucas Stach, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, linux-pci, devicetree,
linux-kernel, linux-arm-kernel, linux-arm-kernel, imx,
Krzysztof Wilczyński
On Wed, Oct 16, 2024 at 11:38:49PM +0530, Manivannan Sadhasivam wrote:
> On Mon, Sep 23, 2024 at 02:59:19PM -0400, Frank Li wrote:
> > Endpoint Root complex
> > ┌───────┐ ┌─────────┐
> > ┌─────┐ │ EP │ │ │ ┌─────┐
> > │ │ │ Ctrl │ │ │ │ CPU │
> > │ DDR │ │ │ │ ┌────┐ │ └──┬──┘
> > │ │◄──────┼─ATU ◄─┼────────┼─┤BarN│◄─┼─────────┘
> > │ │ │ │ │ └────┘ │ Outbound Transfer
> > └─────┘ │ │ │ │
> > │ │ │ │
> > │ │ │ │
> > │ │ │ │ Inbound Transfer
> > │ │ │ │ ┌──▼──┐
> > ┌───────┐ │ │ │ ┌───────┼─────►│DDR │
> > │ │ outbound Transfer* │ │ │ └─────┘
> > ┌─────┐ │ Bus ┼─────►│ ATU ─┬────────┼─┘ │
> > │ │ │ Fabric│Bus │ │ PCI Addr │
> > │ CPU ├───►│ │Addr │ │ 0xA000_0000 │
> > │ │CPU │ │0x8000_0000 │ │ │
> > └─────┘Addr└───────┘ │ │ │ │
> > 0x7000_0000 └───────┘ └─────────┘
> >
> > Add `bus_addr_base` to configure the outbound window address for CPU write.
> > The bus fabric generally passes the same address to the PCIe EP controller,
> > but some bus fabrics convert the address before sending it to the PCIe EP
> > controller.
> >
> > Above diagram, CPU write data to outbound windows address 0x7000_0000,
> > Bus fabric convert it to 0x8000_0000. ATU should use bus address
> > 0x8000_0000 as input address and convert to PCI address 0xA000_0000.
> >
> > Previously, `cpu_addr_fixup()` was used to handle address conversion. Now,
> > the device tree provides this information, preferring a common method.
> >
> > bus@5f000000 {
> > compatible = "simple-bus";
> > ranges = <0x5f000000 0x0 0x5f000000 0x21000000>,
> > <0x80000000 0x0 0x70000000 0x10000000>;
> >
> > pcie-ep@5f010000 {
> > reg = <0x5f010000 0x00010000>,
> > <0x80000000 0x10000000>;
> > reg-names = "dbi", "addr_space";
> > ...
> > };
> > ...
> > };
> >
> > 'ranges' in bus@5f000000 descript how address convert from CPU address
> > to bus address.
> >
> > Use `of_property_read_reg()` to obtain the bus address and set it to the
> > ATU correctly, eliminating the need for vendor-specific cpu_addr_fixup().
> >
> > Signed-off-by: Frank Li <Frank.Li@nxp.com>
> > ---
> > drivers/pci/controller/dwc/pcie-designware-ep.c | 12 +++++++++++-
> > drivers/pci/controller/dwc/pcie-designware.h | 1 +
> > 2 files changed, 12 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
> > index 43ba5c6738df1..51eefdcb1b293 100644
> > --- a/drivers/pci/controller/dwc/pcie-designware-ep.c
> > +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
> > @@ -9,6 +9,7 @@
> > #include <linux/align.h>
> > #include <linux/bitfield.h>
> > #include <linux/of.h>
> > +#include <linux/of_address.h>
> > #include <linux/platform_device.h>
> >
> > #include "pcie-designware.h"
> > @@ -294,7 +295,7 @@ static int dw_pcie_ep_map_addr(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
> >
> > atu.func_no = func_no;
> > atu.type = PCIE_ATU_TYPE_MEM;
> > - atu.cpu_addr = addr;
> > + atu.cpu_addr = addr - ep->phys_base + ep->bus_addr_base;
>
> If you convert the address here, aren't he drivers with cpu_addr_fixup() will be
> broken? You should only update the address if the callback is not available.
Supposed not, ep->phys_base and ep->bus_addr_base should be same when
use cpu_addr_fixup(). but I warry about some old dts have not reflect
hardware bus address translate correct.
How about use below method:
https://lore.kernel.org/imx/20241008-pci_fixup_addr-v4-2-25e5200657bc@nxp.com/
Involve a varible 'using_dtbus_info' to controller it.
Frank
>
> - Mani
>
> > atu.pci_addr = pci_addr;
> > atu.size = size;
> > ret = dw_pcie_ep_outbound_atu(ep, &atu);
> > @@ -861,6 +862,7 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
> > struct device *dev = pci->dev;
> > struct platform_device *pdev = to_platform_device(dev);
> > struct device_node *np = dev->of_node;
> > + int index;
> >
> > INIT_LIST_HEAD(&ep->func_list);
> >
> > @@ -873,6 +875,14 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
> > return -EINVAL;
> >
> > ep->phys_base = res->start;
> > + ep->bus_addr_base = ep->phys_base;
> > +
> > + index = of_property_match_string(np, "reg-names", "addr_space");
> > + if (index < 0)
> > + return -EINVAL;
> > +
> > + of_property_read_reg(np, index, &ep->bus_addr_base, NULL);
> > +
> > ep->addr_size = resource_size(res);
> >
> > if (ep->ops->pre_init)
> > diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
> > index 347ab74ac35aa..c189781524fb8 100644
> > --- a/drivers/pci/controller/dwc/pcie-designware.h
> > +++ b/drivers/pci/controller/dwc/pcie-designware.h
> > @@ -410,6 +410,7 @@ struct dw_pcie_ep {
> > struct list_head func_list;
> > const struct dw_pcie_ep_ops *ops;
> > phys_addr_t phys_base;
> > + phys_addr_t bus_addr_base;
> > size_t addr_size;
> > size_t page_size;
> > u8 bar_to_atu[PCI_STD_NUM_BARS];
> >
> > --
> > 2.34.1
> >
>
> --
> மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v2 2/4] dt-bindings: PCI: fsl,imx6q-pcie-ep: Add compatible string fsl,imx8q-pcie-ep
2024-09-23 18:59 [PATCH v2 0/4] PCI: ep: dwc/imx6: Add bus address support for PCI endpoint devices Frank Li
2024-09-23 18:59 ` [PATCH v2 1/4] PCI: dwc: ep: Add bus_addr_base for outbound window Frank Li
@ 2024-09-23 18:59 ` Frank Li
2024-09-24 16:33 ` Conor Dooley
2024-09-23 18:59 ` [PATCH v2 3/4] PCI: imx6: Pass correct sub mode when calling phy_set_mode_ext() Frank Li
` (2 subsequent siblings)
4 siblings, 1 reply; 14+ messages in thread
From: Frank Li @ 2024-09-23 18:59 UTC (permalink / raw)
To: Lorenzo Pieralisi, Krzysztof Wilczyński,
Manivannan Sadhasivam, Rob Herring, Bjorn Helgaas,
Krzysztof Kozlowski, Conor Dooley, Abraham I, Saravana Kannan,
Jingoo Han, Gustavo Pimentel, Jesper Nilsson, Richard Zhu,
Lucas Stach, Shawn Guo, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam
Cc: linux-pci, devicetree, linux-kernel, linux-arm-kernel,
linux-arm-kernel, imx, Krzysztof Wilczyński, Frank Li
Add new compatible string fsl,imx8q-pcie-ep for iMX8Q. reg-names only needs
'dbi' and 'addr_space' because the others are located at default offset.
The clock-names align Root Complex (RC)'s naming.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
.../devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml | 38 +++++++++++++++++++++-
1 file changed, 37 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml
index 84ca12e8b25be..7bd00faa1f2c3 100644
--- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml
+++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml
@@ -22,6 +22,7 @@ properties:
- fsl,imx8mm-pcie-ep
- fsl,imx8mq-pcie-ep
- fsl,imx8mp-pcie-ep
+ - fsl,imx8q-pcie-ep
- fsl,imx95-pcie-ep
clocks:
@@ -74,6 +75,20 @@ allOf:
- const: dbi2
- const: atu
+ - if:
+ properties:
+ compatible:
+ enum:
+ - fsl,imx8q-pcie-ep
+ then:
+ properties:
+ reg:
+ maxItems: 2
+ reg-names:
+ items:
+ - const: dbi
+ - const: addr_space
+
- if:
properties:
compatible:
@@ -109,7 +124,14 @@ allOf:
- const: pcie_bus
- const: pcie_phy
- const: pcie_aux
- else:
+
+ - if:
+ properties:
+ compatible:
+ enum:
+ - fsl,imx8mm-pcie-ep
+ - fsl,imx8mp-pcie-ep
+ then:
properties:
clocks:
maxItems: 3
@@ -119,6 +141,20 @@ allOf:
- const: pcie_bus
- const: pcie_aux
+ - if:
+ properties:
+ compatible:
+ enum:
+ - fsl,imxq-pcie-ep
+ then:
+ properties:
+ clocks:
+ maxItems: 3
+ clock-names:
+ items:
+ - const: dbi
+ - const: mstr
+ - const: slv
unevaluatedProperties: false
--
2.34.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH v2 2/4] dt-bindings: PCI: fsl,imx6q-pcie-ep: Add compatible string fsl,imx8q-pcie-ep
2024-09-23 18:59 ` [PATCH v2 2/4] dt-bindings: PCI: fsl,imx6q-pcie-ep: Add compatible string fsl,imx8q-pcie-ep Frank Li
@ 2024-09-24 16:33 ` Conor Dooley
0 siblings, 0 replies; 14+ messages in thread
From: Conor Dooley @ 2024-09-24 16:33 UTC (permalink / raw)
To: Frank Li
Cc: Lorenzo Pieralisi, Krzysztof Wilczyński,
Manivannan Sadhasivam, Rob Herring, Bjorn Helgaas,
Krzysztof Kozlowski, Conor Dooley, Abraham I, Saravana Kannan,
Jingoo Han, Gustavo Pimentel, Jesper Nilsson, Richard Zhu,
Lucas Stach, Shawn Guo, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, linux-pci, devicetree, linux-kernel,
linux-arm-kernel, linux-arm-kernel, imx,
Krzysztof Wilczyński
[-- Attachment #1: Type: text/plain, Size: 372 bytes --]
On Mon, Sep 23, 2024 at 02:59:20PM -0400, Frank Li wrote:
> Add new compatible string fsl,imx8q-pcie-ep for iMX8Q. reg-names only needs
> 'dbi' and 'addr_space' because the others are located at default offset.
> The clock-names align Root Complex (RC)'s naming.
>
> Signed-off-by: Frank Li <Frank.Li@nxp.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v2 3/4] PCI: imx6: Pass correct sub mode when calling phy_set_mode_ext()
2024-09-23 18:59 [PATCH v2 0/4] PCI: ep: dwc/imx6: Add bus address support for PCI endpoint devices Frank Li
2024-09-23 18:59 ` [PATCH v2 1/4] PCI: dwc: ep: Add bus_addr_base for outbound window Frank Li
2024-09-23 18:59 ` [PATCH v2 2/4] dt-bindings: PCI: fsl,imx6q-pcie-ep: Add compatible string fsl,imx8q-pcie-ep Frank Li
@ 2024-09-23 18:59 ` Frank Li
2024-09-25 3:06 ` Hongxing Zhu
2024-10-16 18:12 ` Manivannan Sadhasivam
2024-09-23 18:59 ` [PATCH v2 4/4] PCI: imx6: Add i.MX8Q PCIe Endpoint (EP) support Frank Li
2024-10-04 20:24 ` [PATCH v2 0/4] PCI: ep: dwc/imx6: Add bus address support for PCI endpoint devices Frank Li
4 siblings, 2 replies; 14+ messages in thread
From: Frank Li @ 2024-09-23 18:59 UTC (permalink / raw)
To: Lorenzo Pieralisi, Krzysztof Wilczyński,
Manivannan Sadhasivam, Rob Herring, Bjorn Helgaas,
Krzysztof Kozlowski, Conor Dooley, Abraham I, Saravana Kannan,
Jingoo Han, Gustavo Pimentel, Jesper Nilsson, Richard Zhu,
Lucas Stach, Shawn Guo, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam
Cc: linux-pci, devicetree, linux-kernel, linux-arm-kernel,
linux-arm-kernel, imx, Krzysztof Wilczyński, Frank Li
Fix hardcoding to Root Complex (RC) mode by adding a drvdata mode check.
Pass PHY_MODE_PCIE_EP if the PCI controller operates in Endpoint (EP) mode.
Fixes: 8026f2d8e8a9 ("PCI: imx6: Call common PHY API to set mode, speed, and submode")
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
drivers/pci/controller/dwc/pci-imx6.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index 808d1f1054173..bdc2b372e6c13 100644
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -961,7 +961,9 @@ static int imx_pcie_host_init(struct dw_pcie_rp *pp)
goto err_clk_disable;
}
- ret = phy_set_mode_ext(imx_pcie->phy, PHY_MODE_PCIE, PHY_MODE_PCIE_RC);
+ ret = phy_set_mode_ext(imx_pcie->phy, PHY_MODE_PCIE,
+ imx_pcie->drvdata->mode == DW_PCIE_EP_TYPE ?
+ PHY_MODE_PCIE_EP : PHY_MODE_PCIE_RC);
if (ret) {
dev_err(dev, "unable to set PCIe PHY mode\n");
goto err_phy_exit;
--
2.34.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* RE: [PATCH v2 3/4] PCI: imx6: Pass correct sub mode when calling phy_set_mode_ext()
2024-09-23 18:59 ` [PATCH v2 3/4] PCI: imx6: Pass correct sub mode when calling phy_set_mode_ext() Frank Li
@ 2024-09-25 3:06 ` Hongxing Zhu
2024-10-16 18:12 ` Manivannan Sadhasivam
1 sibling, 0 replies; 14+ messages in thread
From: Hongxing Zhu @ 2024-09-25 3:06 UTC (permalink / raw)
To: Frank Li, Lorenzo Pieralisi, Krzysztof Wilczyński,
Manivannan Sadhasivam, Rob Herring, Bjorn Helgaas,
Krzysztof Kozlowski, Conor Dooley, Abraham I, Saravana Kannan,
Jingoo Han, Gustavo Pimentel, Jesper Nilsson, Lucas Stach,
Shawn Guo, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam
Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-arm-kernel@axis.com,
linux-arm-kernel@lists.infradead.org, imx@lists.linux.dev,
Krzysztof Wilczyński
> -----Original Message-----
> From: Frank Li <frank.li@nxp.com>
> Sent: 2024年9月24日 2:59
> To: Lorenzo Pieralisi <lpieralisi@kernel.org>; Krzysztof Wilczyński
> <kw@linux.com>; Manivannan Sadhasivam
> <manivannan.sadhasivam@linaro.org>; Rob Herring <robh@kernel.org>;
> Bjorn Helgaas <bhelgaas@google.com>; Krzysztof Kozlowski
> <krzk+dt@kernel.org>; Conor Dooley <conor+dt@kernel.org>; Abraham I
> <kishon@kernel.org>; Saravana Kannan <saravanak@google.com>; Jingoo
> Han <jingoohan1@gmail.com>; Gustavo Pimentel
> <gustavo.pimentel@synopsys.com>; Jesper Nilsson
> <jesper.nilsson@axis.com>; Hongxing Zhu <hongxing.zhu@nxp.com>; Lucas
> Stach <l.stach@pengutronix.de>; Shawn Guo <shawnguo@kernel.org>;
> Sascha Hauer <s.hauer@pengutronix.de>; Pengutronix Kernel Team
> <kernel@pengutronix.de>; Fabio Estevam <festevam@gmail.com>
> Cc: linux-pci@vger.kernel.org; devicetree@vger.kernel.org;
> linux-kernel@vger.kernel.org; linux-arm-kernel@axis.com;
> linux-arm-kernel@lists.infradead.org; imx@lists.linux.dev; Krzysztof
> Wilczyński <kwilczynski@kernel.org>; Frank Li <frank.li@nxp.com>
> Subject: [PATCH v2 3/4] PCI: imx6: Pass correct sub mode when calling
> phy_set_mode_ext()
>
> Fix hardcoding to Root Complex (RC) mode by adding a drvdata mode check.
> Pass PHY_MODE_PCIE_EP if the PCI controller operates in Endpoint (EP)
> mode.
>
> Fixes: 8026f2d8e8a9 ("PCI: imx6: Call common PHY API to set mode, speed,
> and submode")
> Signed-off-by: Frank Li <Frank.Li@nxp.com>
Reviewed-by: Richard Zhu <hongxing.zhu@nxp.com>
Best Regards
Richard Zhu
> ---
> drivers/pci/controller/dwc/pci-imx6.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/pci/controller/dwc/pci-imx6.c
> b/drivers/pci/controller/dwc/pci-imx6.c
> index 808d1f1054173..bdc2b372e6c13 100644
> --- a/drivers/pci/controller/dwc/pci-imx6.c
> +++ b/drivers/pci/controller/dwc/pci-imx6.c
> @@ -961,7 +961,9 @@ static int imx_pcie_host_init(struct dw_pcie_rp *pp)
> goto err_clk_disable;
> }
>
> - ret = phy_set_mode_ext(imx_pcie->phy, PHY_MODE_PCIE,
> PHY_MODE_PCIE_RC);
> + ret = phy_set_mode_ext(imx_pcie->phy, PHY_MODE_PCIE,
> + imx_pcie->drvdata->mode ==
> DW_PCIE_EP_TYPE ?
> + PHY_MODE_PCIE_EP : PHY_MODE_PCIE_RC);
> if (ret) {
> dev_err(dev, "unable to set PCIe PHY mode\n");
> goto err_phy_exit;
>
> --
> 2.34.1
^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [PATCH v2 3/4] PCI: imx6: Pass correct sub mode when calling phy_set_mode_ext()
2024-09-23 18:59 ` [PATCH v2 3/4] PCI: imx6: Pass correct sub mode when calling phy_set_mode_ext() Frank Li
2024-09-25 3:06 ` Hongxing Zhu
@ 2024-10-16 18:12 ` Manivannan Sadhasivam
1 sibling, 0 replies; 14+ messages in thread
From: Manivannan Sadhasivam @ 2024-10-16 18:12 UTC (permalink / raw)
To: Frank Li
Cc: Lorenzo Pieralisi, Krzysztof Wilczyński, Rob Herring,
Bjorn Helgaas, Krzysztof Kozlowski, Conor Dooley, Abraham I,
Saravana Kannan, Jingoo Han, Gustavo Pimentel, Jesper Nilsson,
Richard Zhu, Lucas Stach, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, linux-pci, devicetree,
linux-kernel, linux-arm-kernel, linux-arm-kernel, imx,
Krzysztof Wilczyński
On Mon, Sep 23, 2024 at 02:59:21PM -0400, Frank Li wrote:
> Fix hardcoding to Root Complex (RC) mode by adding a drvdata mode check.
> Pass PHY_MODE_PCIE_EP if the PCI controller operates in Endpoint (EP) mode.
>
Patch descriptions should fit within 75 columns.
> Fixes: 8026f2d8e8a9 ("PCI: imx6: Call common PHY API to set mode, speed, and submode")
> Signed-off-by: Frank Li <Frank.Li@nxp.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
- Mani
> ---
> drivers/pci/controller/dwc/pci-imx6.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
> index 808d1f1054173..bdc2b372e6c13 100644
> --- a/drivers/pci/controller/dwc/pci-imx6.c
> +++ b/drivers/pci/controller/dwc/pci-imx6.c
> @@ -961,7 +961,9 @@ static int imx_pcie_host_init(struct dw_pcie_rp *pp)
> goto err_clk_disable;
> }
>
> - ret = phy_set_mode_ext(imx_pcie->phy, PHY_MODE_PCIE, PHY_MODE_PCIE_RC);
> + ret = phy_set_mode_ext(imx_pcie->phy, PHY_MODE_PCIE,
> + imx_pcie->drvdata->mode == DW_PCIE_EP_TYPE ?
> + PHY_MODE_PCIE_EP : PHY_MODE_PCIE_RC);
> if (ret) {
> dev_err(dev, "unable to set PCIe PHY mode\n");
> goto err_phy_exit;
>
> --
> 2.34.1
>
--
மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v2 4/4] PCI: imx6: Add i.MX8Q PCIe Endpoint (EP) support
2024-09-23 18:59 [PATCH v2 0/4] PCI: ep: dwc/imx6: Add bus address support for PCI endpoint devices Frank Li
` (2 preceding siblings ...)
2024-09-23 18:59 ` [PATCH v2 3/4] PCI: imx6: Pass correct sub mode when calling phy_set_mode_ext() Frank Li
@ 2024-09-23 18:59 ` Frank Li
2024-09-25 3:05 ` Hongxing Zhu
2024-10-16 18:14 ` Manivannan Sadhasivam
2024-10-04 20:24 ` [PATCH v2 0/4] PCI: ep: dwc/imx6: Add bus address support for PCI endpoint devices Frank Li
4 siblings, 2 replies; 14+ messages in thread
From: Frank Li @ 2024-09-23 18:59 UTC (permalink / raw)
To: Lorenzo Pieralisi, Krzysztof Wilczyński,
Manivannan Sadhasivam, Rob Herring, Bjorn Helgaas,
Krzysztof Kozlowski, Conor Dooley, Abraham I, Saravana Kannan,
Jingoo Han, Gustavo Pimentel, Jesper Nilsson, Richard Zhu,
Lucas Stach, Shawn Guo, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam
Cc: linux-pci, devicetree, linux-kernel, linux-arm-kernel,
linux-arm-kernel, imx, Krzysztof Wilczyński, Frank Li
Add support for i.MX8Q series (i.MX8QM, i.MX8QXP, and i.MX8DXL) PCIe
Endpoint (EP). On i.MX8Q platforms, the PCI bus addresses differ from the
CPU addresses. The DesignWare (DWC) driver already handles this in the
common code.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
drivers/pci/controller/dwc/pci-imx6.c | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index bdc2b372e6c13..1e58c24137e7f 100644
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -70,6 +70,7 @@ enum imx_pcie_variants {
IMX8MQ_EP,
IMX8MM_EP,
IMX8MP_EP,
+ IMX8Q_EP,
IMX95_EP,
};
@@ -1079,6 +1080,16 @@ static const struct pci_epc_features imx8m_pcie_epc_features = {
.align = SZ_64K,
};
+static const struct pci_epc_features imx8q_pcie_epc_features = {
+ .linkup_notifier = false,
+ .msi_capable = true,
+ .msix_capable = false,
+ .bar[BAR_1] = { .type = BAR_RESERVED, },
+ .bar[BAR_3] = { .type = BAR_RESERVED, },
+ .bar[BAR_5] = { .type = BAR_RESERVED, },
+ .align = SZ_64K,
+};
+
/*
* BAR# | Default BAR enable | Default BAR Type | Default BAR Size | BAR Sizing Scheme
* ================================================================================================
@@ -1645,6 +1656,14 @@ static const struct imx_pcie_drvdata drvdata[] = {
.epc_features = &imx8m_pcie_epc_features,
.enable_ref_clk = imx8mm_pcie_enable_ref_clk,
},
+ [IMX8Q_EP] = {
+ .variant = IMX8Q_EP,
+ .flags = IMX_PCIE_FLAG_HAS_PHYDRV,
+ .mode = DW_PCIE_EP_TYPE,
+ .epc_features = &imx8q_pcie_epc_features,
+ .clk_names = imx8q_clks,
+ .clks_cnt = ARRAY_SIZE(imx8q_clks),
+ },
[IMX95_EP] = {
.variant = IMX95_EP,
.flags = IMX_PCIE_FLAG_HAS_SERDES |
@@ -1674,6 +1693,7 @@ static const struct of_device_id imx_pcie_of_match[] = {
{ .compatible = "fsl,imx8mq-pcie-ep", .data = &drvdata[IMX8MQ_EP], },
{ .compatible = "fsl,imx8mm-pcie-ep", .data = &drvdata[IMX8MM_EP], },
{ .compatible = "fsl,imx8mp-pcie-ep", .data = &drvdata[IMX8MP_EP], },
+ { .compatible = "fsl,imx8q-pcie-ep", .data = &drvdata[IMX8Q_EP], },
{ .compatible = "fsl,imx95-pcie-ep", .data = &drvdata[IMX95_EP], },
{},
};
--
2.34.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* RE: [PATCH v2 4/4] PCI: imx6: Add i.MX8Q PCIe Endpoint (EP) support
2024-09-23 18:59 ` [PATCH v2 4/4] PCI: imx6: Add i.MX8Q PCIe Endpoint (EP) support Frank Li
@ 2024-09-25 3:05 ` Hongxing Zhu
2024-10-16 18:14 ` Manivannan Sadhasivam
1 sibling, 0 replies; 14+ messages in thread
From: Hongxing Zhu @ 2024-09-25 3:05 UTC (permalink / raw)
To: Frank Li, Lorenzo Pieralisi, Krzysztof Wilczyński,
Manivannan Sadhasivam, Rob Herring, Bjorn Helgaas,
Krzysztof Kozlowski, Conor Dooley, Abraham I, Saravana Kannan,
Jingoo Han, Gustavo Pimentel, Jesper Nilsson, Lucas Stach,
Shawn Guo, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam
Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-arm-kernel@axis.com,
linux-arm-kernel@lists.infradead.org, imx@lists.linux.dev,
Krzysztof Wilczyński
> -----Original Message-----
> From: Frank Li <frank.li@nxp.com>
> Sent: 2024年9月24日 2:59
> To: Lorenzo Pieralisi <lpieralisi@kernel.org>; Krzysztof Wilczyński
> <kw@linux.com>; Manivannan Sadhasivam
> <manivannan.sadhasivam@linaro.org>; Rob Herring <robh@kernel.org>;
> Bjorn Helgaas <bhelgaas@google.com>; Krzysztof Kozlowski
> <krzk+dt@kernel.org>; Conor Dooley <conor+dt@kernel.org>; Abraham I
> <kishon@kernel.org>; Saravana Kannan <saravanak@google.com>; Jingoo
> Han <jingoohan1@gmail.com>; Gustavo Pimentel
> <gustavo.pimentel@synopsys.com>; Jesper Nilsson
> <jesper.nilsson@axis.com>; Hongxing Zhu <hongxing.zhu@nxp.com>; Lucas
> Stach <l.stach@pengutronix.de>; Shawn Guo <shawnguo@kernel.org>;
> Sascha Hauer <s.hauer@pengutronix.de>; Pengutronix Kernel Team
> <kernel@pengutronix.de>; Fabio Estevam <festevam@gmail.com>
> Cc: linux-pci@vger.kernel.org; devicetree@vger.kernel.org;
> linux-kernel@vger.kernel.org; linux-arm-kernel@axis.com;
> linux-arm-kernel@lists.infradead.org; imx@lists.linux.dev; Krzysztof
> Wilczyński <kwilczynski@kernel.org>; Frank Li <frank.li@nxp.com>
> Subject: [PATCH v2 4/4] PCI: imx6: Add i.MX8Q PCIe Endpoint (EP) support
>
> Add support for i.MX8Q series (i.MX8QM, i.MX8QXP, and i.MX8DXL) PCIe
> Endpoint (EP). On i.MX8Q platforms, the PCI bus addresses differ from the
> CPU addresses. The DesignWare (DWC) driver already handles this in the
> common code.
>
> Signed-off-by: Frank Li <Frank.Li@nxp.com>
Reviewed-by: Richard Zhu <hongxing.zhu@nxp.com>
Best Regards
Richard Zhu
> ---
> drivers/pci/controller/dwc/pci-imx6.c | 20 ++++++++++++++++++++
> 1 file changed, 20 insertions(+)
>
> diff --git a/drivers/pci/controller/dwc/pci-imx6.c
> b/drivers/pci/controller/dwc/pci-imx6.c
> index bdc2b372e6c13..1e58c24137e7f 100644
> --- a/drivers/pci/controller/dwc/pci-imx6.c
> +++ b/drivers/pci/controller/dwc/pci-imx6.c
> @@ -70,6 +70,7 @@ enum imx_pcie_variants {
> IMX8MQ_EP,
> IMX8MM_EP,
> IMX8MP_EP,
> + IMX8Q_EP,
> IMX95_EP,
> };
>
> @@ -1079,6 +1080,16 @@ static const struct pci_epc_features
> imx8m_pcie_epc_features = {
> .align = SZ_64K,
> };
>
> +static const struct pci_epc_features imx8q_pcie_epc_features = {
> + .linkup_notifier = false,
> + .msi_capable = true,
> + .msix_capable = false,
> + .bar[BAR_1] = { .type = BAR_RESERVED, },
> + .bar[BAR_3] = { .type = BAR_RESERVED, },
> + .bar[BAR_5] = { .type = BAR_RESERVED, },
> + .align = SZ_64K,
> +};
> +
> /*
> * BAR# | Default BAR enable | Default BAR Type | Default BAR Size
> | BAR Sizing Scheme
> *
> ==============================================================
> ==================================
> @@ -1645,6 +1656,14 @@ static const struct imx_pcie_drvdata drvdata[] = {
> .epc_features = &imx8m_pcie_epc_features,
> .enable_ref_clk = imx8mm_pcie_enable_ref_clk,
> },
> + [IMX8Q_EP] = {
> + .variant = IMX8Q_EP,
> + .flags = IMX_PCIE_FLAG_HAS_PHYDRV,
> + .mode = DW_PCIE_EP_TYPE,
> + .epc_features = &imx8q_pcie_epc_features,
> + .clk_names = imx8q_clks,
> + .clks_cnt = ARRAY_SIZE(imx8q_clks),
> + },
> [IMX95_EP] = {
> .variant = IMX95_EP,
> .flags = IMX_PCIE_FLAG_HAS_SERDES |
> @@ -1674,6 +1693,7 @@ static const struct of_device_id
> imx_pcie_of_match[] = {
> { .compatible = "fsl,imx8mq-pcie-ep", .data = &drvdata[IMX8MQ_EP], },
> { .compatible = "fsl,imx8mm-pcie-ep", .data = &drvdata[IMX8MM_EP], },
> { .compatible = "fsl,imx8mp-pcie-ep", .data = &drvdata[IMX8MP_EP], },
> + { .compatible = "fsl,imx8q-pcie-ep", .data = &drvdata[IMX8Q_EP], },
> { .compatible = "fsl,imx95-pcie-ep", .data = &drvdata[IMX95_EP], },
> {},
> };
>
> --
> 2.34.1
^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [PATCH v2 4/4] PCI: imx6: Add i.MX8Q PCIe Endpoint (EP) support
2024-09-23 18:59 ` [PATCH v2 4/4] PCI: imx6: Add i.MX8Q PCIe Endpoint (EP) support Frank Li
2024-09-25 3:05 ` Hongxing Zhu
@ 2024-10-16 18:14 ` Manivannan Sadhasivam
1 sibling, 0 replies; 14+ messages in thread
From: Manivannan Sadhasivam @ 2024-10-16 18:14 UTC (permalink / raw)
To: Frank Li
Cc: Lorenzo Pieralisi, Krzysztof Wilczyński, Rob Herring,
Bjorn Helgaas, Krzysztof Kozlowski, Conor Dooley, Abraham I,
Saravana Kannan, Jingoo Han, Gustavo Pimentel, Jesper Nilsson,
Richard Zhu, Lucas Stach, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, linux-pci, devicetree,
linux-kernel, linux-arm-kernel, linux-arm-kernel, imx,
Krzysztof Wilczyński
On Mon, Sep 23, 2024 at 02:59:22PM -0400, Frank Li wrote:
Subject should specify 'i.MX8Q series of SoCs'. So it would become:
'PCI: imx6: Add PCIe Endpoint (EP) support for i.MX8Q series of SoCs'
> Add support for i.MX8Q series (i.MX8QM, i.MX8QXP, and i.MX8DXL) PCIe
> Endpoint (EP). On i.MX8Q platforms, the PCI bus addresses differ from the
> CPU addresses. The DesignWare (DWC) driver already handles this in the
> common code.
>
> Signed-off-by: Frank Li <Frank.Li@nxp.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
- Mani
> ---
> drivers/pci/controller/dwc/pci-imx6.c | 20 ++++++++++++++++++++
> 1 file changed, 20 insertions(+)
>
> diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
> index bdc2b372e6c13..1e58c24137e7f 100644
> --- a/drivers/pci/controller/dwc/pci-imx6.c
> +++ b/drivers/pci/controller/dwc/pci-imx6.c
> @@ -70,6 +70,7 @@ enum imx_pcie_variants {
> IMX8MQ_EP,
> IMX8MM_EP,
> IMX8MP_EP,
> + IMX8Q_EP,
> IMX95_EP,
> };
>
> @@ -1079,6 +1080,16 @@ static const struct pci_epc_features imx8m_pcie_epc_features = {
> .align = SZ_64K,
> };
>
> +static const struct pci_epc_features imx8q_pcie_epc_features = {
> + .linkup_notifier = false,
> + .msi_capable = true,
> + .msix_capable = false,
> + .bar[BAR_1] = { .type = BAR_RESERVED, },
> + .bar[BAR_3] = { .type = BAR_RESERVED, },
> + .bar[BAR_5] = { .type = BAR_RESERVED, },
> + .align = SZ_64K,
> +};
> +
> /*
> * BAR# | Default BAR enable | Default BAR Type | Default BAR Size | BAR Sizing Scheme
> * ================================================================================================
> @@ -1645,6 +1656,14 @@ static const struct imx_pcie_drvdata drvdata[] = {
> .epc_features = &imx8m_pcie_epc_features,
> .enable_ref_clk = imx8mm_pcie_enable_ref_clk,
> },
> + [IMX8Q_EP] = {
> + .variant = IMX8Q_EP,
> + .flags = IMX_PCIE_FLAG_HAS_PHYDRV,
> + .mode = DW_PCIE_EP_TYPE,
> + .epc_features = &imx8q_pcie_epc_features,
> + .clk_names = imx8q_clks,
> + .clks_cnt = ARRAY_SIZE(imx8q_clks),
> + },
> [IMX95_EP] = {
> .variant = IMX95_EP,
> .flags = IMX_PCIE_FLAG_HAS_SERDES |
> @@ -1674,6 +1693,7 @@ static const struct of_device_id imx_pcie_of_match[] = {
> { .compatible = "fsl,imx8mq-pcie-ep", .data = &drvdata[IMX8MQ_EP], },
> { .compatible = "fsl,imx8mm-pcie-ep", .data = &drvdata[IMX8MM_EP], },
> { .compatible = "fsl,imx8mp-pcie-ep", .data = &drvdata[IMX8MP_EP], },
> + { .compatible = "fsl,imx8q-pcie-ep", .data = &drvdata[IMX8Q_EP], },
> { .compatible = "fsl,imx95-pcie-ep", .data = &drvdata[IMX95_EP], },
> {},
> };
>
> --
> 2.34.1
>
--
மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v2 0/4] PCI: ep: dwc/imx6: Add bus address support for PCI endpoint devices
2024-09-23 18:59 [PATCH v2 0/4] PCI: ep: dwc/imx6: Add bus address support for PCI endpoint devices Frank Li
` (3 preceding siblings ...)
2024-09-23 18:59 ` [PATCH v2 4/4] PCI: imx6: Add i.MX8Q PCIe Endpoint (EP) support Frank Li
@ 2024-10-04 20:24 ` Frank Li
2024-10-16 16:20 ` Frank Li
4 siblings, 1 reply; 14+ messages in thread
From: Frank Li @ 2024-10-04 20:24 UTC (permalink / raw)
To: Lorenzo Pieralisi, Krzysztof Wilczyński,
Manivannan Sadhasivam, Rob Herring, Bjorn Helgaas,
Krzysztof Kozlowski, Conor Dooley, Abraham I, Saravana Kannan,
Jingoo Han, Gustavo Pimentel, Jesper Nilsson, Richard Zhu,
Lucas Stach, Shawn Guo, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam
Cc: linux-pci, devicetree, linux-kernel, linux-arm-kernel,
linux-arm-kernel, imx, Krzysztof Wilczyński
On Mon, Sep 23, 2024 at 02:59:18PM -0400, Frank Li wrote:
> Endpoint Root complex
> ┌───────┐ ┌─────────┐
> ┌─────┐ │ EP │ │ │ ┌─────┐
> │ │ │ Ctrl │ │ │ │ CPU │
> │ DDR │ │ │ │ ┌────┐ │ └──┬──┘
> │ │◄──────┼─ATU ◄─┼────────┼─┤BarN│◄─┼─────────┘
> │ │ │ │ │ └────┘ │ Outbound Transfer
> └─────┘ │ │ │ │
> │ │ │ │
> │ │ │ │
> │ │ │ │ Inbound Transfer
> │ │ │ │ ┌──▼──┐
> ┌───────┐ │ │ │ ┌───────┼─────►│DDR │
> │ │ outbound Transfer* │ │ │ └─────┘
> ┌─────┐ │ Bus ┼─────►│ ATU ─┬────────┼─┘ │
> │ │ │ Fabric│Bus │ │ PCI Addr │
> │ CPU ├───►│ │Addr │ │ 0xA000_0000 │
> │ │CPU │ │0x8000_0000 │ │ │
> └─────┘Addr└───────┘ │ │ │ │
> 0x7000_0000 └───────┘ └─────────┘
Manivannan Sadhasivam:
Do you have chance to review these patches?
Frank
>
> Add `bus_addr_base` to configure the outbound window address for CPU write.
> The BUS fabric generally passes the same address to the PCIe EP controller,
> but some BUS fabrics convert the address before sending it to the PCIe EP
> controller.
>
> Above diagram, CPU write data to outbound windows address 0x7000_0000,
> Bus fabric convert it to 0x8000_0000. ATU should use BUS address
> 0x8000_0000 as input address and convert to PCI address 0xA000_0000.
>
> Previously, `cpu_addr_fixup()` was used to handle address conversion. Now,
> the device tree provides this information, preferring a common method.
>
> bus@5f000000 {
> compatible = "simple-bus";
> ranges = <0x5f000000 0x0 0x5f000000 0x21000000>,
> <0x80000000 0x0 0x70000000 0x10000000>;
>
> pcie-ep@5f010000 {
> reg = <0x5f010000 0x00010000>,
> <0x80000000 0x10000000>;
> reg-names = "dbi", "addr_space";
> ...
> };
> ...
> };
>
> 'ranges' in bus@5f000000 descript how address convert from CPU address
> to BUS address.
>
> Use `of_property_read_reg()` to obtain the BUS address and set it to the
> ATU correctly, eliminating the need for vendor-specific cpu_addr_fixup().
>
> The 1st patch implement above method in dwc common driver.
> The 2nd patch update imx6's binding doc to add fsl,imx8q-pcie-ep.
> The 3rd patch fix a pci-mx6's a bug
> The 4th patch enable pci ep function.
>
> The imx8q's dts is usptreaming, the pcie-ep part is below.
>
> hsio_subsys: bus@5f000000 {
> compatible = "simple-bus";
> #address-cells = <1>;
> #size-cells = <1>;
> /* Only supports up to 32bits DMA, map all possible DDR as inbound ranges */
> dma-ranges = <0x80000000 0 0x80000000 0x80000000>;
> ranges = <0x5f000000 0x0 0x5f000000 0x21000000>,
> <0x80000000 0x0 0x70000000 0x10000000>;
>
> pcieb_ep: pcie-ep@5f010000 {
> compatible = "fsl,imx8q-pcie-ep";
> reg = <0x5f010000 0x00010000>,
> <0x80000000 0x10000000>;
> reg-names = "dbi", "addr_space";
> num-lanes = <1>;
> interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
> interrupt-names = "dma";
> clocks = <&pcieb_lpcg IMX_LPCG_CLK_6>,
> <&pcieb_lpcg IMX_LPCG_CLK_4>,
> <&pcieb_lpcg IMX_LPCG_CLK_5>;
> clock-names = "dbi", "mstr", "slv";
> power-domains = <&pd IMX_SC_R_PCIE_B>;
> fsl,max-link-speed = <3>;
> num-ib-windows = <6>;
> num-ob-windows = <6>;
> };
> };
>
> Signed-off-by: Frank Li <Frank.Li@nxp.com>
> ---
> Changes in v2:
> - Totally rewrite with difference method. 'range' should in bus node
> instead pcie-ep node because address convert happen at bus fabric. Needn't
> add 'range' property at pci-ep node.
> - Link to v1: https://lore.kernel.org/r/20240919-pcie_ep_range-v1-0-b3e9d62780b7@nxp.com
>
> ---
> Frank Li (4):
> PCI: dwc: ep: Add bus_addr_base for outbound window
> dt-bindings: PCI: fsl,imx6q-pcie-ep: Add compatible string fsl,imx8q-pcie-ep
> PCI: imx6: Pass correct sub mode when calling phy_set_mode_ext()
> PCI: imx6: Add i.MX8Q PCIe Endpoint (EP) support
>
> .../devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml | 38 +++++++++++++++++++++-
> drivers/pci/controller/dwc/pci-imx6.c | 24 +++++++++++++-
> drivers/pci/controller/dwc/pcie-designware-ep.c | 12 ++++++-
> drivers/pci/controller/dwc/pcie-designware.h | 1 +
> 4 files changed, 72 insertions(+), 3 deletions(-)
> ---
> base-commit: 4ed76e3b7438dd6e3d9b11d6a4cb853a350ec407
> change-id: 20240918-pcie_ep_range-4c5c5e300e19
>
> Best regards,
> ---
> Frank Li <Frank.Li@nxp.com>
>
^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [PATCH v2 0/4] PCI: ep: dwc/imx6: Add bus address support for PCI endpoint devices
2024-10-04 20:24 ` [PATCH v2 0/4] PCI: ep: dwc/imx6: Add bus address support for PCI endpoint devices Frank Li
@ 2024-10-16 16:20 ` Frank Li
0 siblings, 0 replies; 14+ messages in thread
From: Frank Li @ 2024-10-16 16:20 UTC (permalink / raw)
To: Lorenzo Pieralisi, Krzysztof Wilczyński,
Manivannan Sadhasivam, Rob Herring, Bjorn Helgaas,
Krzysztof Kozlowski, Conor Dooley, Abraham I, Saravana Kannan,
Jingoo Han, Gustavo Pimentel, Jesper Nilsson, Richard Zhu,
Lucas Stach, Shawn Guo, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam
Cc: linux-pci, devicetree, linux-kernel, linux-arm-kernel,
linux-arm-kernel, imx, Krzysztof Wilczyński
On Fri, Oct 04, 2024 at 04:24:37PM -0400, Frank Li wrote:
> On Mon, Sep 23, 2024 at 02:59:18PM -0400, Frank Li wrote:
> > Endpoint Root complex
> > ┌───────┐ ┌─────────┐
> > ┌─────┐ │ EP │ │ │ ┌─────┐
> > │ │ │ Ctrl │ │ │ │ CPU │
> > │ DDR │ │ │ │ ┌────┐ │ └──┬──┘
> > │ │◄──────┼─ATU ◄─┼────────┼─┤BarN│◄─┼─────────┘
> > │ │ │ │ │ └────┘ │ Outbound Transfer
> > └─────┘ │ │ │ │
> > │ │ │ │
> > │ │ │ │
> > │ │ │ │ Inbound Transfer
> > │ │ │ │ ┌──▼──┐
> > ┌───────┐ │ │ │ ┌───────┼─────►│DDR │
> > │ │ outbound Transfer* │ │ │ └─────┘
> > ┌─────┐ │ Bus ┼─────►│ ATU ─┬────────┼─┘ │
> > │ │ │ Fabric│Bus │ │ PCI Addr │
> > │ CPU ├───►│ │Addr │ │ 0xA000_0000 │
> > │ │CPU │ │0x8000_0000 │ │ │
> > └─────┘Addr└───────┘ │ │ │ │
> > 0x7000_0000 └───────┘ └─────────┘
>
> Manivannan Sadhasivam:
>
> Do you have chance to review these patches?
Manivannan Sadhasivam:
Do you have chance to review these patches?
Frank
>
> Frank
>
>
> >
> > Add `bus_addr_base` to configure the outbound window address for CPU write.
> > The BUS fabric generally passes the same address to the PCIe EP controller,
> > but some BUS fabrics convert the address before sending it to the PCIe EP
> > controller.
> >
> > Above diagram, CPU write data to outbound windows address 0x7000_0000,
> > Bus fabric convert it to 0x8000_0000. ATU should use BUS address
> > 0x8000_0000 as input address and convert to PCI address 0xA000_0000.
> >
> > Previously, `cpu_addr_fixup()` was used to handle address conversion. Now,
> > the device tree provides this information, preferring a common method.
> >
> > bus@5f000000 {
> > compatible = "simple-bus";
> > ranges = <0x5f000000 0x0 0x5f000000 0x21000000>,
> > <0x80000000 0x0 0x70000000 0x10000000>;
> >
> > pcie-ep@5f010000 {
> > reg = <0x5f010000 0x00010000>,
> > <0x80000000 0x10000000>;
> > reg-names = "dbi", "addr_space";
> > ...
> > };
> > ...
> > };
> >
> > 'ranges' in bus@5f000000 descript how address convert from CPU address
> > to BUS address.
> >
> > Use `of_property_read_reg()` to obtain the BUS address and set it to the
> > ATU correctly, eliminating the need for vendor-specific cpu_addr_fixup().
> >
> > The 1st patch implement above method in dwc common driver.
> > The 2nd patch update imx6's binding doc to add fsl,imx8q-pcie-ep.
> > The 3rd patch fix a pci-mx6's a bug
> > The 4th patch enable pci ep function.
> >
> > The imx8q's dts is usptreaming, the pcie-ep part is below.
> >
> > hsio_subsys: bus@5f000000 {
> > compatible = "simple-bus";
> > #address-cells = <1>;
> > #size-cells = <1>;
> > /* Only supports up to 32bits DMA, map all possible DDR as inbound ranges */
> > dma-ranges = <0x80000000 0 0x80000000 0x80000000>;
> > ranges = <0x5f000000 0x0 0x5f000000 0x21000000>,
> > <0x80000000 0x0 0x70000000 0x10000000>;
> >
> > pcieb_ep: pcie-ep@5f010000 {
> > compatible = "fsl,imx8q-pcie-ep";
> > reg = <0x5f010000 0x00010000>,
> > <0x80000000 0x10000000>;
> > reg-names = "dbi", "addr_space";
> > num-lanes = <1>;
> > interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
> > interrupt-names = "dma";
> > clocks = <&pcieb_lpcg IMX_LPCG_CLK_6>,
> > <&pcieb_lpcg IMX_LPCG_CLK_4>,
> > <&pcieb_lpcg IMX_LPCG_CLK_5>;
> > clock-names = "dbi", "mstr", "slv";
> > power-domains = <&pd IMX_SC_R_PCIE_B>;
> > fsl,max-link-speed = <3>;
> > num-ib-windows = <6>;
> > num-ob-windows = <6>;
> > };
> > };
> >
> > Signed-off-by: Frank Li <Frank.Li@nxp.com>
> > ---
> > Changes in v2:
> > - Totally rewrite with difference method. 'range' should in bus node
> > instead pcie-ep node because address convert happen at bus fabric. Needn't
> > add 'range' property at pci-ep node.
> > - Link to v1: https://lore.kernel.org/r/20240919-pcie_ep_range-v1-0-b3e9d62780b7@nxp.com
> >
> > ---
> > Frank Li (4):
> > PCI: dwc: ep: Add bus_addr_base for outbound window
> > dt-bindings: PCI: fsl,imx6q-pcie-ep: Add compatible string fsl,imx8q-pcie-ep
> > PCI: imx6: Pass correct sub mode when calling phy_set_mode_ext()
> > PCI: imx6: Add i.MX8Q PCIe Endpoint (EP) support
> >
> > .../devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml | 38 +++++++++++++++++++++-
> > drivers/pci/controller/dwc/pci-imx6.c | 24 +++++++++++++-
> > drivers/pci/controller/dwc/pcie-designware-ep.c | 12 ++++++-
> > drivers/pci/controller/dwc/pcie-designware.h | 1 +
> > 4 files changed, 72 insertions(+), 3 deletions(-)
> > ---
> > base-commit: 4ed76e3b7438dd6e3d9b11d6a4cb853a350ec407
> > change-id: 20240918-pcie_ep_range-4c5c5e300e19
> >
> > Best regards,
> > ---
> > Frank Li <Frank.Li@nxp.com>
> >
^ permalink raw reply [flat|nested] 14+ messages in thread