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AJvYcCV8YsX+Dj6GpOsX3LSxg2Y/p9M3Dg8vFNhi72TvOdmdlgGmO72OFiaBYjwUNB/mD/29h581sx7PFhU=@vger.kernel.org X-Gm-Message-State: AOJu0YwvImXWTobVnZMk92Y59cWW9It+tWSycozEKY3O3plxWHdOm8cG tzurvfrTOenXcyT9YXoYBe/mSziW2MidFMvSUNLwyJiquHy8EwxDNQfauNgsGQ== X-Google-Smtp-Source: AGHT+IG3djtkgvDwFjL5SMyfW3qLoXY0CLRwpTQ//e0lJY1MODc0J/w7hgvsNBnFokru+vE1owYtFw== X-Received: by 2002:adf:f886:0:b0:371:8cc3:3995 with SMTP id ffacd0b85a97d-37cc24847f5mr1254992f8f.34.1727251141533; Wed, 25 Sep 2024 00:59:01 -0700 (PDT) Received: from thinkpad ([80.66.138.17]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37cbc31f77esm3313206f8f.108.2024.09.25.00.59.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Sep 2024 00:59:01 -0700 (PDT) Date: Wed, 25 Sep 2024 09:58:59 +0200 From: Manivannan Sadhasivam To: Qiang Yu Cc: Johan Hovold , vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, andersson@kernel.org, konradybcio@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, abel.vesa@linaro.org, quic_msarkar@quicinc.com, quic_devipriy@quicinc.com, dmitry.baryshkov@linaro.org, kw@linux.com, lpieralisi@kernel.org, neil.armstrong@linaro.org, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org Subject: Re: [PATCH v4 6/6] arm64: dts: qcom: x1e80100: Add support for PCIe3 on x1e80100 Message-ID: <20240925075859.4vbb4faaworc6eyz@thinkpad> References: <20240924101444.3933828-1-quic_qianyu@quicinc.com> <20240924101444.3933828-7-quic_qianyu@quicinc.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: On Wed, Sep 25, 2024 at 02:37:41PM +0800, Qiang Yu wrote: > > On 9/24/2024 10:43 PM, Johan Hovold wrote: > > On Tue, Sep 24, 2024 at 03:14:44AM -0700, Qiang Yu wrote: > > > Describe PCIe3 controller and PHY. Also add required system resources like > > > regulators, clocks, interrupts and registers configuration for PCIe3. > > > @@ -2907,6 +2907,208 @@ mmss_noc: interconnect@1780000 { > > > #interconnect-cells = <2>; > > > }; > > > + pcie3: pcie@1bd0000 { > > > + device_type = "pci"; > > > + compatible = "qcom,pcie-x1e80100"; > > > + interrupts = , > > > + , > > > + , > > > + , > > > + , > > > + , > > > + , > > > + , > > > + ; > > > + interrupt-names = "msi0", > > > + "msi1", > > > + "msi2", > > > + "msi3", > > > + "msi4", > > > + "msi5", > > > + "msi6", > > > + "msi7", > > > + "global"; > > This ninth "global" interrupt is not described by the bindings, which > > would also need to be updated. What is it used for? > > As of now, the global interrupts is mainly used to get link up event so > that the device driver can enumerate the PCIe endpoint devices without > user intervention. You can refer to > https://lore.kernel.org/linux-pci/20240828-pci-qcom-hotplug-v4-11-263a385fbbcb@linaro.org. > > I see this global interrupts has been documented in qcom,pcie-sm8450.yaml. > Do I need to move it to qcom,pcie-common.yaml? > No, you need to describe it in qcom,pcie-x1e80100.yaml. - Mani -- மணிவண்ணன் சதாசிவம்