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Date: Wed, 2 Oct 2024 15:09:26 -0500
From: Bjorn Helgaas <helgaas@kernel.org>
To: Ajay Agarwal <ajayagarwal@google.com>
Cc: Ilpo =?utf-8?B?SsOkcnZpbmVu?= <ilpo.jarvinen@linux.intel.com>,
	"David E. Box" <david.e.box@linux.intel.com>,
	Johan Hovold <johan+linaro@kernel.org>,
	Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>,
	Bjorn Helgaas <bhelgaas@google.com>,
	Manu Gautam <manugautam@google.com>,
	Sajid Dalvi <sdalvi@google.com>,
	Heiner Kallweit <hkallweit1@gmail.com>,
	Vidya Sagar <vidyas@nvidia.com>,
	Shuai Xue <xueshuai@linux.alibaba.com>, linux-pci@vger.kernel.org
Subject: Re: [PATCH] PCI/ASPM: Disable L1 before disabling L1ss
Message-ID: <20241002200926.GA268053@bhelgaas>
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In-Reply-To: <20241002181223.GA231923@bhelgaas>

On Wed, Oct 02, 2024 at 01:12:23PM -0500, Bjorn Helgaas wrote:
> On Tue, Oct 01, 2024 at 07:05:18PM +0530, Ajay Agarwal wrote:
> > The current sequence in the driver for L1ss update is as follows.
> > 
> > Disable L1ss
> > Disable L1
> > Enable L1ss as required
> > Enable L1 if required
> > 
> > PCIe spec r6.2, section 5.5.4, recommends that setting either
> > or both of the enable bits for ASPM L1 PM Substates must be done
> > while ASPM L1 is disabled. My interpretation here is that
> > clearing L1ss should also be done when L1 is disabled. Thereby,
> > change the sequence as follows.
> > 
> > Disable L1
> > Disable L1ss
> > Enable L1ss as required
> > Enable L1 if required
> ...

> pcie_config_aspm_link() has a comment ("Spec 2.0 ...") about the
> configuration order, but I'd like to update that, add a section
> reference, and make sure we do the disable in the right order.

Found some language about this in the ASPM Control description in PCIe
r6.2, sec 7.5.3.7, Link Control.

Also in sec 7.9.9.3, Root Complex Link Control, although I don't think
Linux has any support for this register.