From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E40061D1E75; Fri, 25 Oct 2024 21:36:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729892189; cv=none; b=KgjzEVw/4w4ZycajHmBj0lm4w75cVJFfLDxj3UQgYzkIgGUO4zlANpq1Dn5WnBL4ngsmalg5Tn9P35p8BrO96NIWZTfS39enjn3jnYa5dBQn4q2pX76LUxbzzG+Hnxv1lXkwNN/6dIyl+J/+A73w/BfVpdlZ8nOHj+OGBOdlW+Q= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729892189; c=relaxed/simple; bh=0VXLkxh/2Ecsv6rIIKWkGlW2EIFOBXyj7cfyt2r+xLM=; h=Date:From:To:Cc:Subject:Message-ID:MIME-Version:Content-Type: Content-Disposition:In-Reply-To; b=etGObcW1sK9rL6v9aBeOVShVHjDTCFg4t2ZbQxKTIhvYeeJyyTV+R3BUZIH0D3v206hXvzB7AYrg/Ho5of2xjOaBA782pKAD4ufnpWYXRzeqz779wuReMm3yAGYJllhPVlmb9hYIwSdWWSei9EtiWI9kQ8Yl8eSwQjd/k/ciIzA= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Lyf/v0GP; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Lyf/v0GP" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 41AF3C4CECC; Fri, 25 Oct 2024 21:36:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1729892188; bh=0VXLkxh/2Ecsv6rIIKWkGlW2EIFOBXyj7cfyt2r+xLM=; h=Date:From:To:Cc:Subject:In-Reply-To:From; b=Lyf/v0GP/E2zd0MG4qbYJMsm3GH3QEQ2KMOyNh3zfnsWD+lCIlZyurAiQTgGyODMq gpjNp9BULeC1T38Gc+WKexKxJWC0h3XMps1GjZp6U7BJ3JQOqfruzmZ/mtWrEsRJaA /rGTwHlhfo6Div0SvSBfMLULLsudg0gEZf//trY6n13+0FAkwwT2oIWxZNoyE/S5HS imKkGLdyMSS+KgpkS2UuHJNPNzUKE0hrQ/wJGAmHUP8AbFcJBHI1s+LArEiUOQNpxz ZEHXNYhKRCTZVXiAv5XmZzehJkVwV2ZjJj3OlvX4saCmtTiR26pWiPXTaPSOghHnxV BeSsAkGJsW/8w== Date: Fri, 25 Oct 2024 16:36:26 -0500 From: Bjorn Helgaas To: Frank Li Cc: Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Abraham I , Saravana Kannan , Jingoo Han , Gustavo Pimentel , Jesper Nilsson , Richard Zhu , Lucas Stach , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@axis.com, linux-arm-kernel@lists.infradead.org, imx@lists.linux.dev, Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Conor Dooley Subject: Re: [PATCH v4 0/4] PCI: ep: dwc/imx6: Add bus address support for PCI endpoint devices Message-ID: <20241025213626.GA1030542@bhelgaas> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: On Fri, Oct 25, 2024 at 05:05:03PM -0400, Frank Li wrote: > On Fri, Oct 25, 2024 at 03:48:18PM -0500, Bjorn Helgaas wrote: > > On Thu, Oct 24, 2024 at 04:41:42PM -0400, Frank Li wrote: > > > Endpoint Root complex > > > ┌───────┐ ┌─────────┐ > > > ┌─────┐ │ EP │ │ │ ┌─────┐ > > > │ │ │ Ctrl │ │ │ │ CPU │ > > > │ DDR │ │ │ │ ┌────┐ │ └──┬──┘ > > > │ │◄──────┼─ATU ◄─┼────────┼─┤BarN│◄─┼─────────┘ > > > │ │ │ │ │ └────┘ │ Outbound Transfer > > > └─────┘ │ │ │ │ > > > │ │ │ │ > > > │ │ │ │ > > > │ │ │ │ Inbound Transfer > > > │ │ │ │ ┌──▼──┐ > > > ┌───────┐ │ │ │ ┌───────┼─────►│DDR │ > > > │ │ outbound Transfer* │ │ │ └─────┘ > > > ┌─────┐ │ Bus ┼─────►│ ATU ─┬────────┼─┘ │ > > > │ │ │ Fabric│Bus │ │ PCI Addr │ > > > │ CPU ├───►│ │Addr │ │ 0xA000_0000 │ > > > │ │CPU │ │0x8000_0000 │ │ │ > > > └─────┘Addr└───────┘ │ │ │ │ > > > 0x7000_0000 └───────┘ └─────────┘ > > > > > > Add `bus_addr_base` to configure the outbound window address for CPU write. > > > The BUS fabric generally passes the same address to the PCIe EP controller, > > > but some BUS fabrics convert the address before sending it to the PCIe EP > > > controller. > > > > > > Above diagram, CPU write data to outbound windows address 0x7000_0000, > > > Bus fabric convert it to 0x8000_0000. ATU should use BUS address > > > 0x8000_0000 as input address and convert to PCI address 0xA000_0000. > > > > The above doesn't match what's in patch 1/4, and I think the version > > in 1/4 is better, so I'll comment there. > > > > To avoid confusion, it might be better not to duplicate it in 0/4 and > > 1/4. > > Yes, cover letter don't come into git tree. This part is common and > important, It is not good just said ref to patch1 commit message. > > Add do you have addition comment about this and > https://lore.kernel.org/imx/20241015-pci_fixup_addr-v5-0-ced556c85270@nxp.com/T/#t > > The both are the pave the road to clean up pci_fixup_addr(). I think it would be helpful to combine the "PCI: dwc: optimize RC host pci_fixup_addr()" series and the "bus_addr_base" parts of this series together into a single series because they are doing very similar things, and it's easier to review them together. And split the dt-bindings, PHY sub mode, and new endpoint support parts to their own series because they're not related to the address translation changes. Bjorn