From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from frasgout.his.huawei.com (frasgout.his.huawei.com [185.176.79.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9399D26AD4; Wed, 30 Oct 2024 14:57:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.176.79.56 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730300243; cv=none; b=TmMVml5HcqQjy3VPGLQikG19waN6fGWD9RMdPk8Yx1ke8OJfDGxD69qsJGhfM4OyEfDoK2HwjKwuXCW/tdTlthe8409lbTXtrCkYd0m3wjICj6rqAJ6LsEy4ebB6NI0LKrm1j182LACnki+IaI+T/xWT1pHVs+QvS4NJNkf8ua0= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730300243; c=relaxed/simple; bh=NFNwA1nAENuRUepB0mrjvJghMwFFjdV9BjvwSmBmWQU=; h=Date:From:To:CC:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=BG4yzX1EXiv9OP9JI15xdX/vhdIhEw3g0oT2KnYNoNR7Tju8tSYcOi5LsRb5ZHEfRN8Z2+F4uflvytwWr2vj8pX+AgACqS8zSeUehGziCjUJpOyErJ7Hd7Ywo3mVk2phqc5gYxJLUF50Y/JifNCmQLZi5WYsJjuqqxGSgZ/Axo4= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=Huawei.com; spf=pass smtp.mailfrom=huawei.com; arc=none smtp.client-ip=185.176.79.56 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=Huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Received: from mail.maildlp.com (unknown [172.18.186.31]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4Xdqpz1946z6GFD4; Wed, 30 Oct 2024 22:52:27 +0800 (CST) Received: from frapeml500008.china.huawei.com (unknown [7.182.85.71]) by mail.maildlp.com (Postfix) with ESMTPS id 65FF3140158; Wed, 30 Oct 2024 22:57:18 +0800 (CST) Received: from localhost (10.203.177.66) by frapeml500008.china.huawei.com (7.182.85.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Wed, 30 Oct 2024 15:57:17 +0100 Date: Wed, 30 Oct 2024 14:57:15 +0000 From: Jonathan Cameron To: Terry Bowman CC: , , , , , , , , , , , , , , , , Subject: Re: [PATCH v2 03/14] cxl/pci: Introduce helper functions pcie_is_cxl() and pcie_is_cxl_port() Message-ID: <20241030145715.00001d78@Huawei.com> In-Reply-To: <20241025210305.27499-4-terry.bowman@amd.com> References: <20241025210305.27499-1-terry.bowman@amd.com> <20241025210305.27499-4-terry.bowman@amd.com> Organization: Huawei Technologies Research and Development (UK) Ltd. X-Mailer: Claws Mail 4.1.0 (GTK 3.24.33; x86_64-w64-mingw32) Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-Transfer-Encoding: 7bit X-ClientProxiedBy: lhrpeml100012.china.huawei.com (7.191.174.184) To frapeml500008.china.huawei.com (7.182.85.71) On Fri, 25 Oct 2024 16:02:54 -0500 Terry Bowman wrote: > CXL and AER drivers need the ability to identify CXL devices and CXL port > devices. > > First, add set_pcie_cxl() with logic checking for CXL Flexbus DVSEC > presence. The CXL Flexbus DVSEC presence is used because it is required > for all the CXL PCIe devices.[1] > > Add boolean 'struct pci_dev::is_cxl' with the purpose to cache the CXL > Flexbus presence. > > Add pcie_is_cxl() as a macro to return 'struct pci_dev::is_cxl', > > Add pcie_is_cxl_port() to check if a device is a CXL root port, CXL > upstream switch port, or CXL downstream switch port. Also, verify the > CXL extensions DVSEC for port is present.[1] > > [1] CXL 3.1 Spec, 8.1.1 PCIe Designated Vendor-Specific Extended > Capability (DVSEC) ID Assignment, Table 8-2 > > Signed-off-by: Terry Bowman Make sense to improve the trace point info if nothing else. Reviewed-by: Jonathan Cameron