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[209.17.68.221]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-211057d3bb8sm63610785ad.246.2024.11.04.09.02.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 04 Nov 2024 09:02:29 -0800 (PST) Date: Tue, 5 Nov 2024 02:02:28 +0900 From: Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= To: AngeloGioacchino Del Regno Cc: linux-pci@vger.kernel.org, ryder.lee@mediatek.com, jianjun.wang@mediatek.com, lpieralisi@kernel.org, robh@kernel.org, bhelgaas@google.com, matthias.bgg@gmail.com, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kernel@collabora.com, fshao@chromium.org Subject: Re: [PATCH v4 0/2] PCI: mediatek-gen3: Support limiting link speed and width Message-ID: <20241104170228.GB4055778@rocinante> References: <20241104114935.172908-1-angelogioacchino.delregno@collabora.com> <20241104170005.GA4055778@rocinante> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20241104170005.GA4055778@rocinante> Hello, > > Changes in v4: > > - Addressed comments from Jianjun Wang's review on v3 > > > > Changes in v3: > > - Addressed comments from Fei Shao's review on v2 > > > > Changes in v2: > > - Rebased on next-20240917 > > > > This series adds support for limiting the PCI-Express link speed > > (or PCIe gen restriction) and link width (number of lanes) in the > > pcie-mediatek-gen3 driver. > > > > The maximum supported pcie gen is read from the controller itself, > > so defining a max gen through platform data for each SoC is avoided. > > > > Both are done by adding support for the standard devicetree properties > > `max-link-speed` and `num-lanes`. > > > > Please note that changing the bindings is not required, as those do > > already allow specifying those properties for this controller. > > Applied to controller/mediatek, thank you! > > [01/02] PCI: mediatek-gen3: Add support for setting max-link-speed limit > https://git.kernel.org/pci/pci/c/ade7da14954a > > [02/02] PCI: mediatek-gen3: Add support for restricting link width > https://git.kernel.org/pci/pci/c/6e73c5898973 Angelo, I made some small changes to the code, per the suggestions. Let me know if you are fine with these, or not. Thank you! Krzysztof