Re: [PATCH v4 0/2] PCI: mediatek-gen3: Support limiting link speed and width

Krzysztof Wilczyński
2024-11-04T17:02:31Z

Hello,

> > Changes in v4:
> > - Addressed comments from Jianjun Wang's review on v3
> >
> > Changes in v3:
> > - Addressed comments from Fei Shao's review on v2
> >
> > Changes in v2:
> > - Rebased on next-20240917
> >
> > This series adds support for limiting the PCI-Express link speed
> > (or PCIe gen restriction) and link width (number of lanes) in the
> > pcie-mediatek-gen3 driver.
> >
> > The maximum supported pcie gen is read from the controller itself,
> > so defining a max gen through platform data for each SoC is avoided.
> >
> > Both are done by adding support for the standard devicetree properties
> > `max-link-speed` and `num-lanes`.
> >
> > Please note that changing the bindings is not required, as those do
> > already allow specifying those properties for this controller.
>
> Applied to controller/mediatek, thank you!
>
> [01/02] PCI: mediatek-gen3: Add support for setting max-link-speed limit
> https://git.kernel.org/pci/pci/c/ade7da14954a
>
> [02/02] PCI: mediatek-gen3: Add support for restricting link width
> https://git.kernel.org/pci/pci/c/6e73c5898973

Angelo,

I made some small changes to the code, per the suggestions. Let me know if
you are fine with these, or not. Thank you!

Krzysztof