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Wed, 13 Nov 2024 13:11:26 -0800 (PST) X-Google-Smtp-Source: AGHT+IHcnNYHsvq3x3d625NCahmbJAqiMdAoQaQkPCDLvS9tewBxW1j7AU7rltZUYu0Dp25868Fj8g== X-Received: by 2002:a05:6e02:194d:b0:3a6:c23b:5aa9 with SMTP id e9e14a558f8ab-3a6f1a58b22mr59857625ab.4.1731532285757; Wed, 13 Nov 2024 13:11:25 -0800 (PST) Received: from redhat.com ([38.15.36.11]) by smtp.gmail.com with ESMTPSA id e9e14a558f8ab-3a6f983826csm31967665ab.27.2024.11.13.13.11.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Nov 2024 13:11:25 -0800 (PST) Date: Wed, 13 Nov 2024 14:11:22 -0700 From: Alex Williamson To: Jason Gunthorpe Cc: Nicolin Chen , tglx@linutronix.de, Robin Murphy , maz@kernel.org, bhelgaas@google.com, leonro@nvidia.com, shameerali.kolothum.thodi@huawei.com, dlemoal@kernel.org, kevin.tian@intel.com, smostafa@google.com, andriy.shevchenko@linux.intel.com, reinette.chatre@intel.com, eric.auger@redhat.com, ddutile@redhat.com, yebin10@huawei.com, brauner@kernel.org, apatel@ventanamicro.com, shivamurthy.shastri@linutronix.de, anna-maria@linutronix.de, nipun.gupta@amd.com, marek.vasut+renesas@mailbox.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, kvm@vger.kernel.org Subject: Re: [PATCH RFCv1 0/7] vfio: Allow userspace to specify the address for each MSI vector Message-ID: <20241113141122.2518c55a.alex.williamson@redhat.com> In-Reply-To: <20241113013430.GC35230@nvidia.com> References: <20241113013430.GC35230@nvidia.com> X-Mailer: Claws Mail 4.3.0 (GTK 3.24.43; x86_64-redhat-linux-gnu) Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit On Tue, 12 Nov 2024 21:34:30 -0400 Jason Gunthorpe wrote: > On Tue, Nov 12, 2024 at 01:54:58PM -0800, Nicolin Chen wrote: > > On Mon, Nov 11, 2024 at 01:09:20PM +0000, Robin Murphy wrote: > > > On 2024-11-09 5:48 am, Nicolin Chen wrote: > > > > To solve this problem the VMM should capture the MSI IOVA allocated by the > > > > guest kernel and relay it to the GIC driver in the host kernel, to program > > > > the correct MSI IOVA. And this requires a new ioctl via VFIO. > > > > > > Once VFIO has that information from userspace, though, do we really need > > > the whole complicated dance to push it right down into the irqchip layer > > > just so it can be passed back up again? AFAICS > > > vfio_msi_set_vector_signal() via VFIO_DEVICE_SET_IRQS already explicitly > > > rewrites MSI-X vectors, so it seems like it should be pretty > > > straightforward to override the message address in general at that > > > level, without the lower layers having to be aware at all, no? > > > > Didn't see that clearly!! It works with a simple following override: > > -------------------------------------------------------------------- > > @@ -497,6 +497,10 @@ static int vfio_msi_set_vector_signal(struct vfio_pci_core_device *vdev, > > struct msi_msg msg; > > > > get_cached_msi_msg(irq, &msg); > > + if (vdev->msi_iovas) { > > + msg.address_lo = lower_32_bits(vdev->msi_iovas[vector]); > > + msg.address_hi = upper_32_bits(vdev->msi_iovas[vector]); > > + } > > pci_write_msi_msg(irq, &msg); > > } > > > > -------------------------------------------------------------------- > > > > With that, I think we only need one VFIO change for this part :) > > Wow, is that really OK from a layering perspective? The comment is > pretty clear on the intention that this is to resync the irq layer > view of the device with the physical HW. > > Editing the msi_msg while doing that resync smells bad. > > Also, this is only doing MSI-X, we should include normal MSI as > well. (it probably should have a resync too?) This was added for a specific IBM HBA that clears the vector table during a built-in self test, so it's possible the MSI table being in config space never had the same issue, or we just haven't encountered it. I don't expect anything else actually requires this. > I'd want Thomas/Marc/Alex to agree.. (please read the cover letter for > context) It seems suspect to me too. In a sense it is still just synchronizing the MSI address, but to a different address space. Is it possible to do this with the existing write_msi_msg callback on the msi descriptor? For instance we could simply translate the msg address and call pci_write_msi_msg() (while avoiding an infinite recursion). Or maybe there should be an xlate_msi_msg callback we can register. Or I suppose there might be a way to insert an irqchip that does the translation on write. Thanks, Alex