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charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20241106221341.2218416-2-quic_mrana@quicinc.com> On Wed, Nov 06, 2024 at 02:13:38PM -0800, Mayank Rana wrote: > To allow dwc PCIe controller based MSI functionality from ECAM pcie > driver, export dw_pcie_msi_host_init(), dw_pcie_msi_init() and > dw_pcie_msi_free() APIs. Also move MSI IRQ related initialization code > into dw_pcie_msi_init() as this code executes before dw_pcie_msi_init() > API to use with ECAM driver. > > Signed-off-by: Mayank Rana > --- > .../pci/controller/dwc/pcie-designware-host.c | 38 ++++++++++--------- > drivers/pci/controller/dwc/pcie-designware.h | 14 +++++++ > 2 files changed, 34 insertions(+), 18 deletions(-) > > diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c > index 3e41865c7290..25020a090db8 100644 > --- a/drivers/pci/controller/dwc/pcie-designware-host.c > +++ b/drivers/pci/controller/dwc/pcie-designware-host.c > @@ -250,7 +250,7 @@ int dw_pcie_allocate_domains(struct dw_pcie_rp *pp) > return 0; > } > > -static void dw_pcie_free_msi(struct dw_pcie_rp *pp) > +void dw_pcie_free_msi(struct dw_pcie_rp *pp) > { > u32 ctrl; > > @@ -263,19 +263,34 @@ static void dw_pcie_free_msi(struct dw_pcie_rp *pp) > irq_domain_remove(pp->msi_domain); > irq_domain_remove(pp->irq_domain); > } > +EXPORT_SYMBOL_GPL(dw_pcie_free_msi); > > -static void dw_pcie_msi_init(struct dw_pcie_rp *pp) > +void dw_pcie_msi_init(struct dw_pcie_rp *pp) > { > struct dw_pcie *pci = to_dw_pcie_from_pp(pp); > u64 msi_target = (u64)pp->msi_data; > + u32 ctrl, num_ctrls; > > if (!pci_msi_enabled() || !pp->has_msi_ctrl) > return; > > + num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL; > + > + /* Initialize IRQ Status array */ > + for (ctrl = 0; ctrl < num_ctrls; ctrl++) { > + dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK + > + (ctrl * MSI_REG_CTRL_BLOCK_SIZE), > + pp->irq_mask[ctrl]); > + dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_ENABLE + > + (ctrl * MSI_REG_CTRL_BLOCK_SIZE), > + ~0); > + } > + > /* Program the msi_data */ > dw_pcie_writel_dbi(pci, PCIE_MSI_ADDR_LO, lower_32_bits(msi_target)); > dw_pcie_writel_dbi(pci, PCIE_MSI_ADDR_HI, upper_32_bits(msi_target)); > } > +EXPORT_SYMBOL_GPL(dw_pcie_msi_init); > > static int dw_pcie_parse_split_msi_irq(struct dw_pcie_rp *pp) > { > @@ -317,7 +332,7 @@ static int dw_pcie_parse_split_msi_irq(struct dw_pcie_rp *pp) > return 0; > } > > -static int dw_pcie_msi_host_init(struct dw_pcie_rp *pp) > +int dw_pcie_msi_host_init(struct dw_pcie_rp *pp) > { > struct dw_pcie *pci = to_dw_pcie_from_pp(pp); > struct device *dev = pci->dev; > @@ -391,6 +406,7 @@ static int dw_pcie_msi_host_init(struct dw_pcie_rp *pp) > > return 0; > } > +EXPORT_SYMBOL_GPL(dw_pcie_msi_host_init); > > static void dw_pcie_host_request_msg_tlp_res(struct dw_pcie_rp *pp) > { > @@ -802,7 +818,7 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp) > int dw_pcie_setup_rc(struct dw_pcie_rp *pp) > { > struct dw_pcie *pci = to_dw_pcie_from_pp(pp); > - u32 val, ctrl, num_ctrls; > + u32 val; > int ret; > > /* > @@ -813,20 +829,6 @@ int dw_pcie_setup_rc(struct dw_pcie_rp *pp) > > dw_pcie_setup(pci); > > - if (pp->has_msi_ctrl) { > - num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL; > - > - /* Initialize IRQ Status array */ > - for (ctrl = 0; ctrl < num_ctrls; ctrl++) { > - dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK + > - (ctrl * MSI_REG_CTRL_BLOCK_SIZE), > - pp->irq_mask[ctrl]); > - dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_ENABLE + > - (ctrl * MSI_REG_CTRL_BLOCK_SIZE), > - ~0); > - } > - } > - > dw_pcie_msi_init(pp); > > /* Setup RC BARs */ > diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h > index 347ab74ac35a..ef748d82c663 100644 > --- a/drivers/pci/controller/dwc/pcie-designware.h > +++ b/drivers/pci/controller/dwc/pcie-designware.h > @@ -679,6 +679,9 @@ static inline enum dw_pcie_ltssm dw_pcie_get_ltssm(struct dw_pcie *pci) > > #ifdef CONFIG_PCIE_DW_HOST > irqreturn_t dw_handle_msi_irq(struct dw_pcie_rp *pp); > +void dw_pcie_msi_init(struct dw_pcie_rp *pp); > +int dw_pcie_msi_host_init(struct dw_pcie_rp *pp); > +void dw_pcie_free_msi(struct dw_pcie_rp *pp); > int dw_pcie_setup_rc(struct dw_pcie_rp *pp); > int dw_pcie_host_init(struct dw_pcie_rp *pp); > void dw_pcie_host_deinit(struct dw_pcie_rp *pp); > @@ -691,6 +694,17 @@ static inline irqreturn_t dw_handle_msi_irq(struct dw_pcie_rp *pp) > return IRQ_NONE; > } > > +static void dw_pcie_msi_init(struct dw_pcie_rp *pp) Missing 'inline' here and below? - Mani > +{ } > + > +static int dw_pcie_msi_host_init(struct dw_pcie_rp *pp) > +{ > + return -ENODEV; > +} > + > +static void dw_pcie_free_msi(struct dw_pcie_rp *pp) > +{ } > + > static inline int dw_pcie_setup_rc(struct dw_pcie_rp *pp) > { > return 0; > -- > 2.25.1 > -- மணிவண்ணன் சதாசிவம்