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[209.17.68.221]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-724771e2c17sm3340248b3a.160.2024.11.16.10.37.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 16 Nov 2024 10:37:54 -0800 (PST) Date: Sun, 17 Nov 2024 03:37:52 +0900 From: Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= To: Manivannan Sadhasivam Cc: Niklas Cassel , Jingoo Han , Lorenzo Pieralisi , Rob Herring , Bjorn Helgaas , Damien Le Moal , Frank Li , linux-pci@vger.kernel.org Subject: Re: [PATCH] PCI: dwc: ep: Do not map more memory than needed to raise a MSI/MSI-X IRQ Message-ID: <20241116183752.GB890334@rocinante> References: <20241104205144.409236-2-cassel@kernel.org> <20241115071924.jn3xun6luqzd2ylp@thinkpad> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20241115071924.jn3xun6luqzd2ylp@thinkpad> Hello, > > In dw_pcie_ep_init() we allocate memory from the EPC address space that we > > will later use to raise a MSI/MSI-X IRQ. This memory is only freed in > > dw_pcie_ep_deinit(). > > > > Performing this allocation in dw_pcie_ep_init() is to ensure that we will > > not fail to allocate memory from the EPC address space when trying to raise > > a MSI/MSI-X IRQ. > > > > We still map/unmap this memory every time we raise an IRQ, in order to not > > constantly occupy an iATU, especially for controllers with few iATUs. > > (So we can still fail to raise an MSI/MSI-X IRQ if all iATUs are occupied.) > > > > When allocating this memory in dw_pcie_ep_init(), we allocate > > epc->mem->window.page_size memory, which is the smallest unit that we can > > allocate from the EPC address space. > > > > However, when writing/sending the msg data, which is only 2 bytes for MSI, > > 4 bytes for MSI-X, in either case a single writel() is sufficient. Thus, > > the size that we need to map is a single PCI DWORD (4 bytes). > > > > This is the size that we should send in to the pci_epc_ops::align_addr() > > API. It is align_addr()'s responsibility to return a size that is aligned > > to the EPC page size, for platforms that need a special alignment. > > > > Modify the align_addr() call to send in the proper size that we need to > > map. > > > > Before this patch on a system with a EPC page size 64k, we would > > incorrectly map 128k (which is larger than our allocation) instead of 64k. > > > > After this patch, we will correctly map 64k (a single page). (We should > > never need to map more than a page to write a single DWORD.) > > > > Fixes: f68da9a67173 ("PCI: dwc: ep: Use align addr function for dw_pcie_ep_raise_{msi,msix}_irq()") > > Signed-off-by: Niklas Cassel > > FWIW, > > Reviewed-by: Manivannan Sadhasivam Picked this tag, too. Thank you! Krzysztof