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charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: On Fri, Nov 15, 2024 at 10:28:23AM -0800, Mayank Rana wrote: > > > On 11/15/2024 3:25 AM, Manivannan Sadhasivam wrote: > > On Wed, Nov 06, 2024 at 02:13:41PM -0800, Mayank Rana wrote: > > > On SA8255p ride platform, PCIe root complex is firmware managed as well > > > configured into ECAM compliant mode. This change adds functionality to > > > enable resource management (system resource as well PCIe controller and > > > PHY configuration) through firmware, and enumerating ECAM compliant root > > > complex. > > > > > > Signed-off-by: Mayank Rana > > > --- > > > drivers/pci/controller/dwc/Kconfig | 1 + > > > drivers/pci/controller/dwc/pcie-qcom.c | 116 +++++++++++++++++++++++-- > > > 2 files changed, 108 insertions(+), 9 deletions(-) > > > > > > diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig > > > index b6d6778b0698..0fe76bd39d69 100644 > > > --- a/drivers/pci/controller/dwc/Kconfig > > > +++ b/drivers/pci/controller/dwc/Kconfig > > > @@ -275,6 +275,7 @@ config PCIE_QCOM > > > select PCIE_DW_HOST > > > select CRC8 > > > select PCIE_QCOM_COMMON > > > + select PCI_HOST_COMMON > > > help > > > Say Y here to enable PCIe controller support on Qualcomm SoCs. The > > > PCIe controller uses the DesignWare core plus Qualcomm-specific > > > diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c > > > index ef44a82be058..2cb74f902baf 100644 > > > --- a/drivers/pci/controller/dwc/pcie-qcom.c > > > +++ b/drivers/pci/controller/dwc/pcie-qcom.c > > > @@ -21,7 +21,9 @@ > > > #include > > > #include > > > #include > > > +#include > > > #include > > > +#include > > > #include > > > #include > > > #include > > > @@ -254,10 +256,12 @@ struct qcom_pcie_ops { > > > * @ops: qcom PCIe ops structure > > > * @override_no_snoop: Override NO_SNOOP attribute in TLP to enable cache > > > * snooping > > > + * @firmware_managed: Set if PCIe root complex is firmware managed > > > > ecam_compliant? > I assume you mean to update as Set if ECAM compliant PCIe root complex is > firmware manage > > > */ > > > struct qcom_pcie_cfg { > > > const struct qcom_pcie_ops *ops; > > > bool override_no_snoop; > > > + bool firmware_managed; > > > bool no_l0s; > > > }; > > > @@ -1415,6 +1419,10 @@ static const struct qcom_pcie_cfg cfg_sc8280xp = { > > > .no_l0s = true, > > > }; > > > +static const struct qcom_pcie_cfg cfg_fw_managed = { > > > > cfg_ecam? > Putting more emphasize on fw_managed as don't want to conflict with new work > in progress (krishna is working on it) > to make Qualcomm PCIe root complex as ECAM compliant (non firmware managed > one). are you OK with using cfg_ecam_fw_managed ? > Ah, I completely missed that. Ignore my comments about renaming to ecam. > > > + .firmware_managed = true, > > > +}; > > > + [...] > > > + /* Parse and map our Configuration Space windows */ > > > + cfg = gen_pci_init(dev, bridge, &pci_qcom_ecam_ops); > > > + if (IS_ERR(cfg)) { > > > + ret = PTR_ERR(cfg); > > > + goto err_pm_runtime_put; > > > + } > > > + > > > + bridge->sysdata = cfg; > > > + bridge->ops = (struct pci_ops *)&pci_qcom_ecam_ops.pci_ops; > > > + bridge->msi_domain = true; > > > + > > > + ret = pci_host_probe(bridge); > > > > return pci_host_probe()... > need to perform pm_runtime_put_sync() and pm_runtime_disable() in failure > case. > Hence checking error here and doing goto err_pm_runtime_put Right. This one I overlooked. - Mani -- மணிவண்ணன் சதாசிவம்