Re: [PATCH v3 1/6] dt-bindings: PCI: Add binding for qps615

Krishna Chaitanya Chundru
2024-12-24T09:11:29Z

On 12/5/2024 2:55 AM, Bjorn Helgaas wrote:
> On Tue, Nov 12, 2024 at 08:31:33PM +0530, Krishna chaitanya chundru wrote:
>> Add binding describing the Qualcomm PCIe switch, QPS615,
>> which provides Ethernet MAC integrated to the 3rd downstream port
>> and two downstream PCIe ports.
>
>> +$defs:
>> + qps615-node:
>> + type: object
>> +
>> + properties:
>> + qcom,l0s-entry-delay-ns:
>> + description: Aspm l0s entry delay.
>> +
>> + qcom,l1-entry-delay-ns:
>> + description: Aspm l1 entry delay.
>
> To match spec usage:
> s/Aspm/ASPM/
> s/l0s/L0s/
> s/l1/L1/
>
> Other than the fact that qps615 needs the driver to configure these,
> there's nothing qcom-specific here, so I suggest the names should omit
> "qcom" and include "aspm".
>
>> + pcie {
>> + #address-cells = <3>;
>> + #size-cells = <2>;
>> +
>> + pcie@0 {
>> + device_type = "pci";
>> + reg = <0x0 0x0 0x0 0x0 0x0>;
>> +
>> + #address-cells = <3>;
>> + #size-cells = <2>;
>> + ranges;
>> + bus-range = <0x01 0xff>;
>> +
>> + pcie@0,0 {
>> + compatible = "pci1179,0623";
>> + reg = <0x10000 0x0 0x0 0x0 0x0>;
>> + device_type = "pci";
>> + #address-cells = <3>;
>> + #size-cells = <2>;
>> + ranges;
>> + bus-range = <0x02 0xff>;
>
> This binding describes a switch. I don't think bus-range should
> appear here at all because it is not a feature of the hardware (unless
> the switch ports are broken and their Secondary/Subordinate Bus
> Numbers are hard-wired).
>
> The Primary/Secondary/Subordinate Bus Numbers of all switch ports
> should be writable and the PCI core knows how to manage them.
>
Bjorn,

The dt binding check is throwing an error if we don't keep bus-range
property for that reason we added it, from dt binding perspective i
think it is mandatory to add this property.

- Krishna Chaitanya.
> Bjorn