Re: [PATCH v4 12/15] cxl/pci: Add error handler for CXL PCIe Port RAS errors

Jonathan Cameron
2024-12-24T18:43:54Z

On Wed, 11 Dec 2024 17:39:59 -0600
Terry Bowman <terry.bowman@amd.com> wrote:

> Introduce correctable and uncorrectable CXL PCIe port protocol error
> handlers.
>
> The handlers will be called with a 'struct pci_dev' parameter
> indicating the CXL Port device requiring handling. The CXL PCIe Port
> device's underlying 'struct device' will match the Port device in the
> CXL topology.
>
> Use the PCIe Port's device object to find the matching Upstream Switch
> Port, Downstream Switch Port, or Root Port in the CXL topology. The
> matching device will contain a reference to the RAS register block used to
> handle and log the error.
>
> Invoke the existing __cxl_handle_ras() or __cxl_handle_cor_ras() passing
> a reference to the RAS registers as a parameter. These functions will use
> the register reference to clear the device's RAS status.
>
> Future patches will assign the error handlers and add trace logging.
>
> Signed-off-by: Terry Bowman <terry.bowman@amd.com>
Other than Li Ming's question, LGTM
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>