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Tue, 17 Dec 2024 09:25:12 -0800 (PST) Date: Tue, 17 Dec 2024 22:55:02 +0530 From: Manivannan Sadhasivam To: Christian Bruel Cc: Bjorn Helgaas , Rob Herring , lpieralisi@kernel.org, kw@linux.com, bhelgaas@google.com, krzk+dt@kernel.org, conor+dt@kernel.org, mcoquelin.stm32@gmail.com, alexandre.torgue@foss.st.com, p.zabel@pengutronix.de, cassel@kernel.org, quic_schintav@quicinc.com, fabrice.gasnier@foss.st.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2 1/5] dt-bindings: PCI: Add STM32MP25 PCIe root complex bindings Message-ID: <20241217172502.borj2oy4rpxcteag@thinkpad> References: <20241205172022.GA3053765@bhelgaas> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: On Tue, Dec 17, 2024 at 04:53:48PM +0100, Christian Bruel wrote: > > > Makes sense. What about phys, resets, etc? I'm pretty sure a PHY > > would be a per-Root Port thing, and some resets and wakeup signals > > also. > > > > For new drivers, I think we should start adding Root Port stanzas to > > specifically associate those things with the Root Port, e.g., > > something like this? > > > > pcie@48400000 { > > compatible = "st,stm32mp25-pcie-rc"; > > > > pcie@0,0 { > > reg = <0x0000 0 0 0 0>; > > phys = <&combophy PHY_TYPE_PCIE>; > > phy-names = "pcie-phy"; > > }; > > }; > > > > https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/pci/mediatek,mt7621-pcie.yaml?id=v6.12#n111 > > is one binding that does this, others include apple,pcie.yaml, > > brcm,stb-pcie.yaml, hisilicon,kirin-pcie.yaml. > > > > On a second thought, moving the PHY to the root-port part would introduce a > discrepancy with the pcie_ep binding, whereas the PHY is required on the > pcie_ep node. > > Even for the pcie_rc, the PHY is needed to enable the core_clk to access > the PCIe core registers, > But why that matters? You can still parse the child nodes, enable PHY and configure PCIe registers. > So that would make 2 different required PHY locations for RC and EP: > > pcie_rc: pcie@48400000 { > compatible = "st,stm32mp25-pcie-rc"; > > pcie@0,0 { > reg = <0x0000 0 0 0 0>; > phys = <&combophy PHY_TYPE_PCIE>; > phy-names = "pcie-phy"; > }; > }; > > pcie_ep pcie@48400000 { > compatible = "st,stm32mp25-pcie-ep"; > phys = <&combophy PHY_TYPE_PCIE>; > phy-names = "pcie-phy"; > }; > > Simplest seems to keep the PHY required for the pcie core regardless of the > mode and keep the empty root port to split the design > No please. Try to do the right thing from the start itself. - Mani -- மணிவண்ணன் சதாசிவம்