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[209.17.68.221]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-219dc9cdf18sm14414725ad.153.2024.12.19.08.37.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Dec 2024 08:37:06 -0800 (PST) Date: Fri, 20 Dec 2024 01:37:05 +0900 From: Krzysztof Wilczy??ski To: Ilpo =?utf-8?B?SsOkcnZpbmVu?= Cc: Lukas Wunner , Bjorn Helgaas , linux-pci@vger.kernel.org, Niklas Schnelle , Jonathan Cameron , Mika Westerberg , "Maciej W. Rozycki" , Mario Limonciello Subject: Re: [PATCH for-linus v3 1/2] PCI: Honor Max Link Speed when determining supported speeds Message-ID: <20241219163705.GA623969@rocinante> References: <7bbd48eb-efaf-260f-ad8d-9fe7f2209812@linux.intel.com> <20241218234357.GA1444967@rocinante> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Hello, [...] > > > > Thanks for adding this extra information. > > > > > > > > I'd also add reference to r6.2 section 7.5.3 which states those registers > > > > are required for RPs, Switch Ports, Bridges, and Endpoints _that are not > > > > RCiEPs_. My reading is that implies they're not required from RCiEPs. > > > > > > Let me know how you would like to update the commit message. I will do it > > > directly on the branch. > > > > FWIW, I edited the commit message like this on my local branch: > > > > -Endpoints in particular, so it does occur in practice. > > +Endpoints in particular, so it does occur in practice. (The Link > > +Capabilities Register is optional on RCiEPs per PCIe r6.2 sec 7.5.3.) > > > > In other words, I just added the sentence in parentheses. > > But maybe Ilpo has another wording preference... :) > > Your wording is good summary for the real substance that is the spec > itself. :-) Updated. Thank you both! Krzysztof