From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from frasgout.his.huawei.com (frasgout.his.huawei.com [185.176.79.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 813A817BED0; Tue, 24 Dec 2024 18:31:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.176.79.56 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735065091; cv=none; b=W+tNacjxzYCjkonrVQSsUtIVd8fFDra9CnMe++BbJW2sZ6HJi/Wi2o4y105NdoU3a/t+gAYDsOwXDEAXVgWmjfWtffep/hM7sYMBuif/LemGwpRJ4RVbUtvbt9ZZxbEj6aa61FBKNN2uZ0kBq3r4OT+yCR4LQU1xzrUz5YBC/IU= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735065091; c=relaxed/simple; bh=SXY+5XuLOjtSM64TsI9tk1lGzvWElQWP/yTqiUYqSHA=; h=Date:From:To:CC:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=cZTF+H0SodVxONDONF4VLnudBrdcvDR9+cb3jSShYAnOTi5hG6Pu9wUc341iMlr6aS8AgEE2pfTI0Nhr42ICxFQdghYuLlUT5q+D+V4+cAM5MFioe4nzIo2sYbaJYZMMTAOTLRqLCf9V7uxbU/7hio9IFS4O+83hqqoJneDjpEs= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; arc=none smtp.client-ip=185.176.79.56 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Received: from mail.maildlp.com (unknown [172.18.186.231]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4YHjzm4CYRz6K5ql; Wed, 25 Dec 2024 02:27:32 +0800 (CST) Received: from frapeml500008.china.huawei.com (unknown [7.182.85.71]) by mail.maildlp.com (Postfix) with ESMTPS id 27BAA140736; Wed, 25 Dec 2024 02:31:26 +0800 (CST) Received: from localhost (10.48.156.150) by frapeml500008.china.huawei.com (7.182.85.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Tue, 24 Dec 2024 19:31:25 +0100 Date: Tue, 24 Dec 2024 18:31:22 +0000 From: Jonathan Cameron To: Terry Bowman CC: , , , , , , , , , , , , , , , , , , , Subject: Re: [PATCH v4 07/15] PCI/AER: Add CXL PCIe Port Uncorrectable Error recovery in AER service driver Message-ID: <20241224183122.00004cf4@huawei.com> In-Reply-To: <20241211234002.3728674-8-terry.bowman@amd.com> References: <20241211234002.3728674-1-terry.bowman@amd.com> <20241211234002.3728674-8-terry.bowman@amd.com> X-Mailer: Claws Mail 4.3.0 (GTK 3.24.42; x86_64-w64-mingw32) Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: lhrpeml100001.china.huawei.com (7.191.160.183) To frapeml500008.china.huawei.com (7.182.85.71) On Wed, 11 Dec 2024 17:39:54 -0600 Terry Bowman wrote: > Existing recovery procedure for PCIe Uncorrectable Errors (UCE) does not > apply to CXL devices. Recovery can not be used for CXL devices because of > potential corruption on what can be system memory. Also, current PCIe UCE > recovery, in the case of a Root Port (RP) or Downstream Switch Port (DSP), > does not begin at the RP/DSP but begins at the first downstream device. > This will miss handling CXL Protocol Errors in a CXL RP or DSP. A separate > CXL recovery is needed because of the different handling requirements >=20 > Add a new function, cxl_do_recovery() using the following. >=20 > Add cxl_walk_bridge() to iterate the detected error's sub-topology. > cxl_walk_bridge() is similar to pci_walk_bridge() but the CXL flavor > will begin iteration at the RP or DSP rather than beginning at the > first downstream device. I'm still not keen on this just from a subtlety making maintenance harder point of view. Guess I should find the time to make the change to the PCI walker and see if anyone shouts that it is a problem. =46rom other branch of thread sounds like you are reworking this patch anyway so I'll wait for next version before reviewing closely. Jonathan >=20 > Add cxl_report_error_detected() as an analog to report_error_detected(). > It will call pci_driver::cxl_err_handlers for each iterated downstream > device. The pci_driver::cxl_err_handler's UCE handler returns a boolean > indicating if there was a UCE error detected during handling. >=20 > cxl_do_recovery() uses the status from cxl_report_error_detected() to > determine how to proceed. Non-fatal CXL UCE errors will be treated as > fatal. If a UCE was present during handling then cxl_do_recovery() > will kernel panic. >=20 > Signed-off-by: Terry Bowman