From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from frasgout.his.huawei.com (frasgout.his.huawei.com [185.176.79.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8C8CC1465B4; Tue, 24 Dec 2024 18:46:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.176.79.56 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735065972; cv=none; b=XZMNXzTjKN/ugNROeessPkoWIV3itENllM2kVCAIGiu1kIvxnECujBULIc0wt8/g6Q3TzNpQgLnWTDHwLDmCk7PKNULdu4nTNLAGCdsTBDqlqwKY35xXohm03G/Lnc7fIl4PYm91gtz8TFCtvtkXaUPXn8XIycPNcOuFcg3yJ7k= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735065972; c=relaxed/simple; bh=nzirmFDxk0CBE3+MUiOqMNcDEgch4eMrxiygnLelkmc=; h=Date:From:To:CC:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=IMVk3/D1hHehskxaP/QlY9Mrq/BbPQAlwXGYXtRqoFPd1dSU8sii+WkID2hezGBZpMUcae4Jt/ipLvlkX3J9eLOdCtgO6+mJ0p7kT4v7iT4WRlyvrhSwJuWhKOF8nKJDzpE44gX2OlcpWnHfjtlhL+sPD5g91wUHg/zNCBhX4zw= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; arc=none smtp.client-ip=185.176.79.56 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Received: from mail.maildlp.com (unknown [172.18.186.216]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4YHkMq0KpZz6LDGm; Wed, 25 Dec 2024 02:44:55 +0800 (CST) Received: from frapeml500008.china.huawei.com (unknown [7.182.85.71]) by mail.maildlp.com (Postfix) with ESMTPS id AEB87140133; Wed, 25 Dec 2024 02:46:08 +0800 (CST) Received: from localhost (10.48.156.150) by frapeml500008.china.huawei.com (7.182.85.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Tue, 24 Dec 2024 19:46:07 +0100 Date: Tue, 24 Dec 2024 18:46:05 +0000 From: Jonathan Cameron To: Terry Bowman CC: , , , , , , , , , , , , , , , , , , , Subject: Re: [PATCH v4 13/15] cxl/pci: Add trace logging for CXL PCIe Port RAS errors Message-ID: <20241224184605.00001e5f@huawei.com> In-Reply-To: <20241211234002.3728674-14-terry.bowman@amd.com> References: <20241211234002.3728674-1-terry.bowman@amd.com> <20241211234002.3728674-14-terry.bowman@amd.com> X-Mailer: Claws Mail 4.3.0 (GTK 3.24.42; x86_64-w64-mingw32) Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-Transfer-Encoding: 7bit X-ClientProxiedBy: lhrpeml100001.china.huawei.com (7.191.160.183) To frapeml500008.china.huawei.com (7.182.85.71) On Wed, 11 Dec 2024 17:40:00 -0600 Terry Bowman wrote: > The CXL drivers use kernel trace functions for logging endpoint and RCH > Downstream Port RAS errors. Similar functionality is required for CXL Root > Ports, CXL Downstream Switch Ports, and CXL Upstream Switch Ports. > > Introduce trace logging functions for both RAS correctable and > uncorrectable errors specific to CXL PCIe Ports. Additionally, update > the PCIe Port error handlers to invoke these new trace functions. > > Signed-off-by: Terry Bowman Trivial comment inline. Reviewed-by: Jonathan Cameron > --- > drivers/cxl/core/pci.c | 16 ++++++++++---- > drivers/cxl/core/trace.h | 47 ++++++++++++++++++++++++++++++++++++++++ > 2 files changed, 59 insertions(+), 4 deletions(-) > > diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c > index 52afaedf5171..3294ad5ff28f 100644 > --- a/drivers/cxl/core/pci.c > +++ b/drivers/cxl/core/pci.c > @@ -661,10 +661,14 @@ static void __cxl_handle_cor_ras(struct device *dev, > > addr = ras_base + CXL_RAS_CORRECTABLE_STATUS_OFFSET; > status = readl(addr); > - if (status & CXL_RAS_CORRECTABLE_STATUS_MASK) { > - writel(status & CXL_RAS_CORRECTABLE_STATUS_MASK, addr); > + if (!(status & CXL_RAS_CORRECTABLE_STATUS_MASK)) > + return; I'd put a blank line here. > + writel(status & CXL_RAS_CORRECTABLE_STATUS_MASK, addr); > + > + if (is_cxl_memdev(dev)) > trace_cxl_aer_correctable_error(to_cxl_memdev(dev), status); > - } > + else > + trace_cxl_port_aer_correctable_error(dev, status); > } > > static void cxl_handle_endpoint_cor_ras(struct cxl_dev_state *cxlds) > @@ -720,7 +724,11 @@ static bool __cxl_handle_ras(struct device *dev, void __iomem *ras_base) > } > > header_log_copy(ras_base, hl); > - trace_cxl_aer_uncorrectable_error(to_cxl_memdev(dev), status, fe, hl); > + if (is_cxl_memdev(dev)) > + trace_cxl_aer_uncorrectable_error(to_cxl_memdev(dev), status, fe, hl); > + else > + trace_cxl_port_aer_uncorrectable_error(dev, status, fe, hl); > + > writel(status & CXL_RAS_UNCORRECTABLE_STATUS_MASK, addr); > > return true;