From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
To: Brian Norris <briannorris@chromium.org>
Cc: "Jingoo Han" <jingoohan1@gmail.com>,
"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Bjorn Helgaas" <bhelgaas@google.com>,
linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org,
"Rob Herring" <robh@kernel.org>,
"Marc Zyngier" <marc.zyngier@arm.com>,
"Krzysztof Wilczyński" <kw@linux.com>,
"Brian Norris" <briannorris@google.com>
Subject: Re: [PATCH] PCI: dwc: Use level-triggered handler for MSI IRQs
Date: Mon, 30 Dec 2024 22:41:45 +0530 [thread overview]
Message-ID: <20241230171145.hsqynixmowjn77ki@thinkpad> (raw)
In-Reply-To: <20241015141215.1.Id60295bee6aacf44aa3664e702012cb4710529c3@changeid>
On Tue, Oct 15, 2024 at 02:12:16PM -0700, Brian Norris wrote:
> From: Brian Norris <briannorris@google.com>
>
> Per Synopsis's documentation, the msi_ctrl_int signal is
> level-triggered, not edge-triggered.
>
Could you please quote the spec reference?
- Mani
> The use of handle_edge_trigger() was chosen in commit 7c5925afbc58
> ("PCI: dwc: Move MSI IRQs allocation to IRQ domains hierarchical API"),
> which actually dropped preexisting use of handle_level_trigger().
> Looking at the patch history, this change was only made by request:
>
> Subject: Re: [PATCH v6 1/9] PCI: dwc: Add IRQ chained API support
> https://lore.kernel.org/all/04d3d5b6-9199-218d-476f-c77d04b8d2e7@arm.com/
>
> "Are you sure about this "handle_level_irq"? MSIs are definitely edge
> triggered, not level."
>
> However, while the underlying MSI protocol is edge-triggered in a sense,
> the DesignWare IP is actually level-triggered.
>
> So, let's switch back to level-triggered.
>
> In many cases, the distinction doesn't really matter here, because this
> signal is hidden behind another (chained) top-level IRQ which can be
> masked on its own. But it's still wise to manipulate this interrupt line
> according to its actual specification -- specifically, to mask it while
> we handle it.
>
> Signed-off-by: Brian Norris <briannorris@google.com>
> Signed-off-by: Brian Norris <briannorris@chromium.org>
> ---
>
> drivers/pci/controller/dwc/pcie-designware-host.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
> index 3e41865c7290..0fb79a26d05e 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-host.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-host.c
> @@ -198,7 +198,7 @@ static int dw_pcie_irq_domain_alloc(struct irq_domain *domain,
> for (i = 0; i < nr_irqs; i++)
> irq_domain_set_info(domain, virq + i, bit + i,
> pp->msi_irq_chip,
> - pp, handle_edge_irq,
> + pp, handle_level_irq,
> NULL, NULL);
>
> return 0;
> --
> 2.47.0.rc1.288.g06298d1525-goog
>
--
மணிவண்ணன் சதாசிவம்
next prev parent reply other threads:[~2024-12-30 17:11 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-15 21:12 [PATCH] PCI: dwc: Use level-triggered handler for MSI IRQs Brian Norris
2024-12-30 17:11 ` Manivannan Sadhasivam [this message]
2025-01-03 1:43 ` Brian Norris
2025-01-03 17:49 ` Bjorn Helgaas
2025-01-03 17:58 ` Bjorn Helgaas
2025-01-03 22:47 ` Brian Norris
2025-01-04 10:09 ` Manivannan Sadhasivam
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