Re: [PATCH] PCI: dwc: Use level-triggered handler for MSI IRQs

[Bjorn Helgaas <helgaas@kernel.org>]

On Fri, Jan 03, 2025 at 11:49:57AM -0600, Bjorn Helgaas wrote:
> On Thu, Jan 02, 2025 at 05:43:26PM -0800, Brian Norris wrote:
> > On Mon, Dec 30, 2024 at 10:41:45PM +0530, Manivannan Sadhasivam wrote:
> > > On Tue, Oct 15, 2024 at 02:12:16PM -0700, Brian Norris wrote:
> > > > From: Brian Norris <briannorris@google.com>
> > > > 
> > > > Per Synopsis's documentation, the msi_ctrl_int signal is
> > > > level-triggered, not edge-triggered.
> > > 
> > > Could you please quote the spec reference?
> > 
> > From the reference manual for msi_ctrl_int:
> > 
> >   "Asserted when an MSI interrupt is pending. De-asserted when there is
> >   no MSI interrupt pending.
> >   ...
> >   Active State: High (level)"
> > 
> > The reference manual also points at the databook for more info. One
> > relevant excerpt from the databook:
> > 
> >   "When any status bit remains set, then msi_ctrl_int remains asserted.
> >   The interrupt status register provides a status bit for up to 32
> >   interrupt vectors per Endpoint. When the decoded interrupt vector is
> >   enabled but is masked, then the controller sets the corresponding bit
> >   in interrupt status register but the it does not assert the top-level
> >   controller output msi_ctrl_int.
> 
> "the it" might be a transcription error?
> 
> > That's essentially a prose description of level-triggering, plus
> > 32-vector multiplexing and masking.
> > 
> > Did you want a v2 with this included, or did you just want it noted
> > here?
> 
> I think a v2 with citations (spec name, revision, section number)
> would be helpful.  Including these quotes as well would be fine with
> me.

Oh, and it would be awesome if we can motivate this patch by mentioning
an actual problem it can avoid.

It sounds like there really *is* a problem at least in some
topologies, so I think we should describe that problem before
explaining why we haven't seen it yet.

> > (Side note: I think it doesn't really matter that much whether we use
> > the 'level' or 'edge' variant handlers here, at least if the parent
> > interrupt is configured correctly as level-triggered. We're not actually
> > in danger of a level-triggered interrupt flood or similar issue.)
> > 
> > Brian