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From: Terry Bowman <terry.bowman@amd.com>
To: <linux-cxl@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
	<linux-pci@vger.kernel.org>, <nifan.cxl@gmail.com>,
	<dave@stgolabs.net>, <jonathan.cameron@huawei.com>,
	<dave.jiang@intel.com>, <alison.schofield@intel.com>,
	<vishal.l.verma@intel.com>, <dan.j.williams@intel.com>,
	<bhelgaas@google.com>, <mahesh@linux.ibm.com>,
	<ira.weiny@intel.com>, <oohall@gmail.com>,
	<Benjamin.Cheatham@amd.com>, <rrichter@amd.com>,
	<nathan.fontenot@amd.com>, <terry.bowman@amd.com>,
	<Smita.KoralahalliChannabasappa@amd.com>, <lukas@wunner.de>,
	<ming.li@zohomail.com>, <PradeepVineshReddy.Kodamati@amd.com>,
	<alucerop@amd.com>
Subject: [PATCH v5 06/16] PCI/AER: Change AER driver to read UCE fatal status for all CXL PCIe Port devices
Date: Tue, 7 Jan 2025 08:38:42 -0600	[thread overview]
Message-ID: <20250107143852.3692571-7-terry.bowman@amd.com> (raw)
In-Reply-To: <20250107143852.3692571-1-terry.bowman@amd.com>

The AER service driver's aer_get_device_error_info() function doesn't read
uncorrectable (UCE) fatal error status from PCIe Upstream Port devices,
including CXL Upstream Switch Ports. As a result, fatal errors are not
logged or handled as needed for CXL PCIe Upstream Switch Port devices.

Update the aer_get_device_error_info() function to read the UCE fatal
status for all CXL PCIe devices. Make the change such that non-CXL devices
are not affected.

The fatal error status will be used in future patches implementing
CXL PCIe Port uncorrectable error handling and logging.

Signed-off-by: Terry Bowman <terry.bowman@amd.com>
---
 drivers/pci/pcie/aer.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c
index 62be599e3bee..79c828bdcb6d 100644
--- a/drivers/pci/pcie/aer.c
+++ b/drivers/pci/pcie/aer.c
@@ -1253,7 +1253,8 @@ int aer_get_device_error_info(struct pci_dev *dev, struct aer_err_info *info)
 	} else if (type == PCI_EXP_TYPE_ROOT_PORT ||
 		   type == PCI_EXP_TYPE_RC_EC ||
 		   type == PCI_EXP_TYPE_DOWNSTREAM ||
-		   info->severity == AER_NONFATAL) {
+		   info->severity == AER_NONFATAL ||
+		   (pcie_is_cxl(dev) && type == PCI_EXP_TYPE_UPSTREAM)) {
 
 		/* Link is still healthy for IO reads */
 		pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS,
-- 
2.34.1


  parent reply	other threads:[~2025-01-07 14:40 UTC|newest]

Thread overview: 96+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-01-07 14:38 [PATCH v5 0/16] Enable CXL PCIe port protocol error handling and logging Terry Bowman
2025-01-07 14:38 ` [PATCH v5 01/16] PCI/AER: Introduce 'struct cxl_err_handlers' and add to 'struct pci_driver' Terry Bowman
2025-01-13 23:45   ` Ira Weiny
2025-02-06 17:01   ` Gregory Price
2025-02-07 18:35     ` Bowman, Terry
2025-01-07 14:38 ` [PATCH v5 02/16] PCI/AER: Rename AER driver's interfaces to also indicate CXL PCIe Port support Terry Bowman
2025-01-13 23:45   ` Ira Weiny
2025-02-06 17:02   ` Gregory Price
2025-01-07 14:38 ` [PATCH v5 03/16] CXL/PCI: Introduce PCIe helper functions pcie_is_cxl() and pcie_is_cxl_port() Terry Bowman
2025-01-13 23:49   ` Ira Weiny
2025-01-14 15:19     ` Bowman, Terry
2025-01-14 23:33       ` Ira Weiny
2025-01-14 23:39         ` Bowman, Terry
2025-01-16 15:35           ` Ira Weiny
2025-01-15 10:03       ` Lukas Wunner
2025-01-07 14:38 ` [PATCH v5 04/16] PCI/AER: Modify AER driver logging to report CXL or PCIe bus error type Terry Bowman
2025-01-13 23:51   ` Ira Weiny
2025-02-06 18:18   ` Gregory Price
2025-02-07 18:50     ` Bowman, Terry
2025-01-07 14:38 ` [PATCH v5 05/16] PCI/AER: Add CXL PCIe Port correctable error support in AER service driver Terry Bowman
2025-01-14  6:54   ` Li Ming
2025-01-14 11:20     ` Jonathan Cameron
2025-01-14 20:10       ` Bowman, Terry
2025-01-14 19:29     ` Bowman, Terry
2025-01-15  1:18       ` Li Ming
2025-01-15 14:39         ` Bowman, Terry
2025-01-16  3:15           ` Li Ming
2025-02-05  3:46             ` Bowman, Terry
2025-02-05 13:58               ` Li Ming
2025-02-05 14:22                 ` Bowman, Terry
2025-01-14 16:35   ` Ira Weiny
2025-02-06 18:33   ` Gregory Price
2025-02-07 17:54     ` Jonathan Cameron
2025-02-07 19:05     ` Bowman, Terry
2025-01-07 14:38 ` Terry Bowman [this message]
2025-01-14 11:32   ` [PATCH v5 06/16] PCI/AER: Change AER driver to read UCE fatal status for all CXL PCIe Port devices Jonathan Cameron
2025-01-14 20:44     ` Bowman, Terry
2025-01-28 20:25     ` Bowman, Terry
2025-01-29 18:04       ` Jonathan Cameron
2025-01-14 16:57   ` Ira Weiny
2025-01-07 14:38 ` [PATCH v5 07/16] PCI/AER: Add CXL PCIe Port uncorrectable error recovery in AER service driver Terry Bowman
2025-01-14 11:33   ` Jonathan Cameron
2025-01-14 20:28     ` Bowman, Terry
2025-01-15 11:37       ` Jonathan Cameron
2025-01-14 17:27   ` Ira Weiny
2025-01-07 14:38 ` [PATCH v5 08/16] cxl/pci: Map CXL PCIe Root Port and Downstream Switch Port RAS registers Terry Bowman
2025-01-14 21:37   ` Ira Weiny
2025-02-07  7:30   ` Gregory Price
2025-02-07 19:08     ` Bowman, Terry
2025-02-07 19:39       ` Gregory Price
2025-01-07 14:38 ` [PATCH v5 09/16] cxl/pci: Map CXL PCIe Upstream " Terry Bowman
2025-01-14 11:35   ` Jonathan Cameron
2025-01-14 15:24     ` Bowman, Terry
2025-01-14 22:02   ` Ira Weiny
2025-01-14 22:11     ` Bowman, Terry
2025-01-14 23:38       ` Ira Weiny
2025-01-14 23:49         ` Bowman, Terry
2025-01-15 11:40           ` Jonathan Cameron
2025-02-07  7:35   ` Gregory Price
2025-01-07 14:38 ` [PATCH v5 10/16] cxl/pci: Update RAS handler interfaces to also support CXL PCIe Ports Terry Bowman
2025-01-14 11:39   ` Jonathan Cameron
2025-01-14 22:20   ` Ira Weiny
2025-02-07  7:38   ` Gregory Price
2025-01-07 14:38 ` [PATCH v5 11/16] cxl/pci: Add log message for umnapped registers in existing RAS handlers Terry Bowman
2025-01-14 11:41   ` Jonathan Cameron
2025-01-14 22:21   ` Ira Weiny
2025-02-07  7:39   ` Gregory Price
2025-01-07 14:38 ` [PATCH v5 12/16] cxl/pci: Change find_cxl_port() to non-static Terry Bowman
2025-01-14 22:23   ` Ira Weiny
2025-02-07  7:45     ` Gregory Price
2025-01-07 14:38 ` [PATCH v5 13/16] cxl/pci: Add error handler for CXL PCIe Port RAS errors Terry Bowman
2025-01-14 11:46   ` Jonathan Cameron
2025-01-14 21:20     ` Bowman, Terry
2025-01-14 22:51   ` Ira Weiny
2025-01-14 23:10     ` Bowman, Terry
2025-01-14 23:42     ` Bowman, Terry
2025-02-07  8:01   ` Gregory Price
2025-02-07 19:23     ` Bowman, Terry
2025-02-07 19:41       ` Gregory Price
2025-02-07 21:04         ` Bowman, Terry
2025-01-07 14:38 ` [PATCH v5 14/16] cxl/pci: Add trace logging " Terry Bowman
2025-01-14 11:49   ` Jonathan Cameron
2025-01-14 20:56     ` Bowman, Terry
2025-01-15 11:42       ` Jonathan Cameron
2025-01-14 22:58   ` Ira Weiny
2025-01-07 14:38 ` [PATCH v5 15/16] cxl/pci: Add support to assign and clear pci_driver::cxl_err_handlers Terry Bowman
2025-01-14 11:51   ` Jonathan Cameron
2025-01-14 23:03   ` Ira Weiny
2025-02-07  8:08   ` Gregory Price
2025-01-07 14:38 ` [PATCH v5 16/16] PCI/AER: Enable internal errors for CXL Upstream and Downstream Switch Ports Terry Bowman
2025-01-14 23:26   ` Ira Weiny
2025-01-14 23:34     ` Bowman, Terry
2025-01-14 23:45       ` Ira Weiny
2025-01-15  0:09         ` Bowman, Terry
2025-01-15  0:20         ` Bowman, Terry
2025-01-16 21:42           ` Ira Weiny

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