From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
To: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Cc: "Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Krzysztof Wilczyński" <kw@linux.com>,
"Rob Herring" <robh@kernel.org>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
"Conor Dooley" <conor+dt@kernel.org>,
"Mrinmay Sarkar" <quic_msarkar@quicinc.com>,
"Bjorn Andersson" <andersson@kernel.org>,
"Konrad Dybcio" <konradybcio@kernel.org>,
"Krzysztof Wilczyński" <kwilczynski@kernel.org>,
"Krzysztof Kozlowski" <krzysztof.kozlowski@linaro.org>,
linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 1/6] dt-bindings: PCI: qcom-ep: describe optional IOMMU
Date: Thu, 20 Feb 2025 12:49:43 +0530 [thread overview]
Message-ID: <20250220071943.edn6q65ijmeldnag@thinkpad> (raw)
In-Reply-To: <20250217-sar2130p-pci-v1-1-94b20ec70a14@linaro.org>
On Mon, Feb 17, 2025 at 08:56:13PM +0200, Dmitry Baryshkov wrote:
> Platforms which use eDMA for PCIe EP transfers (like SA8775P) also use
> IOMMU in order to setup transfer windows.
eDMA has nothing to do with IOMMU. In fact, it is not clear on what IOMMU does
on the endpoint side since we do not assign SID based on the RID from RC.
But the binding should describe it anyway since IOMMU does sit between DDR and
PCIe IP.
- Mani
> Fix the schema in order to
> allow specifying the IOMMU.
>
> Fixes: 9d3d5e75f31c ("dt-bindings: PCI: qcom-ep: Add support for SA8775P SoC")
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml | 17 +++++++++++++++++
> 1 file changed, 17 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml
> index 1226ee5d08d1ae909b07b0d78014618c4c74e9a8..800accdf5947e7178ad80f0759cf53111be1a814 100644
> --- a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml
> +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml
> @@ -75,6 +75,9 @@ properties:
> - const: doorbell
> - const: dma
>
> + iommus:
> + maxItems: 1
> +
> reset-gpios:
> description: GPIO used as PERST# input signal
> maxItems: 1
> @@ -233,6 +236,20 @@ allOf:
> minItems: 3
> maxItems: 3
>
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: qcom,sdx55-pcie-ep
> + then:
> + properties:
> + iommus:
> + false
> +
> + else:
> + required:
> + - iommus
> +
> unevaluatedProperties: false
>
> examples:
>
> --
> 2.39.5
>
--
மணிவண்ணன் சதாசிவம்
next prev parent reply other threads:[~2025-02-20 7:19 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-17 18:56 [PATCH 0/6] PCI: qcom-ep: add support for using the EP on SAR2130P and SM8450 Dmitry Baryshkov
2025-02-17 18:56 ` [PATCH 1/6] dt-bindings: PCI: qcom-ep: describe optional IOMMU Dmitry Baryshkov
2025-02-20 7:19 ` Manivannan Sadhasivam [this message]
2025-02-21 0:41 ` Dmitry Baryshkov
2025-02-17 18:56 ` [PATCH 2/6] dt-bindings: PCI: qcom-ep: enable DMA for SM8450 Dmitry Baryshkov
2025-02-20 7:20 ` Manivannan Sadhasivam
2025-02-17 18:56 ` [PATCH 3/6] dt-bindings: PCI: qcom-ep: add SAR2130P compatible Dmitry Baryshkov
2025-02-20 7:21 ` Manivannan Sadhasivam
2025-02-17 18:56 ` [PATCH 4/6] PCI: dwc: pcie-qcom-ep: enable EP support for SAR2130P Dmitry Baryshkov
2025-02-20 7:23 ` Manivannan Sadhasivam
2025-02-20 10:50 ` Dmitry Baryshkov
2025-02-21 19:23 ` Konrad Dybcio
2025-02-17 18:56 ` [PATCH 5/6] arm64: dts: qcom: sar2130p: add PCIe EP device nodes Dmitry Baryshkov
2025-02-17 19:23 ` Konrad Dybcio
2025-02-18 3:11 ` Dmitry Baryshkov
2025-02-18 13:10 ` Konrad Dybcio
2025-02-17 18:56 ` [PATCH 6/6] arm64: dts: qcom: sm8450: " Dmitry Baryshkov
2025-02-17 20:37 ` Konrad Dybcio
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