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From: Niklas Cassel <cassel@kernel.org>
To: Bjorn Helgaas <bhelgaas@google.com>
Cc: "Manivannan Sadhasivam" <manivannan.sadhasivam@linaro.org>,
	"Krzysztof Wilczyński" <kwilczynski@kernel.org>,
	"Shawn Lin" <shawn.lin@rock-chips.com>,
	"Niklas Cassel" <cassel@kernel.org>,
	linux-pci@vger.kernel.org
Subject: [PATCH] PCI: dwc: Add rockchip to the RAS DES allowed vendor list
Date: Tue, 25 Feb 2025 15:56:58 +0100	[thread overview]
Message-ID: <20250225145657.944925-2-cassel@kernel.org> (raw)

Add PCI_VENDOR_ID_ROCKCHIP to the list of RAS DES vendor specific ids.

Tested using the RAS DES DWC debugfs changes that was merged recently.

drivers/perf/dwc_pcie_pmu.c driver has not been tested, but considering
RAS DES works in DWC debugfs, I see no reason why RAS DES shouldn't work
in drivers/perf/dwc_pcie_pmu.c.

Signed-off-by: Niklas Cassel <cassel@kernel.org>
---
Note: this depends on DWC debugfs patches that are queued up in branch
      controller/dwc and the PCI_VENDOR_ID_ROCKCHIP patch on branch
      controller/rockchip.

 include/linux/pcie-dwc.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/linux/pcie-dwc.h b/include/linux/pcie-dwc.h
index 6436e7fadc75..15d27a509769 100644
--- a/include/linux/pcie-dwc.h
+++ b/include/linux/pcie-dwc.h
@@ -28,6 +28,8 @@ static const struct dwc_pcie_vsec_id dwc_pcie_rasdes_vsec_ids[] = {
 	  .vsec_id = 0x02, .vsec_rev = 0x4 },
 	{ .vendor_id = PCI_VENDOR_ID_QCOM,
 	  .vsec_id = 0x02, .vsec_rev = 0x4 },
+	{ .vendor_id = PCI_VENDOR_ID_ROCKCHIP,
+	  .vsec_id = 0x02, .vsec_rev = 0x4 },
 	{ .vendor_id = PCI_VENDOR_ID_SAMSUNG,
 	  .vsec_id = 0x02, .vsec_rev = 0x4 },
 	{} /* terminator */
-- 
2.48.1


             reply	other threads:[~2025-02-25 14:57 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-02-25 14:56 Niklas Cassel [this message]
2025-02-26 14:36 ` [PATCH] PCI: dwc: Add rockchip to the RAS DES allowed vendor list Krzysztof Wilczyński

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