Re: [PATCH v7 3/5] Add debugfs based silicon debug support in DWC

Fan Ni
2025-03-03T17:48:30Z

On Fri, Feb 21, 2025 at 06:45:46PM +0530, Shradha Todi wrote:
> Add support to provide silicon debug interface to userspace. This set
> of debug registers are part of the RASDES feature present in DesignWare
> PCIe controllers.
>
> Signed-off-by: Shradha Todi <shradha.t@samsung.com>

One comment inline.
> ---
> Documentation/ABI/testing/debugfs-dwc-pcie | 13 ++
> drivers/pci/controller/dwc/Kconfig | 10 +
> drivers/pci/controller/dwc/Makefile | 1 +
> .../controller/dwc/pcie-designware-debugfs.c | 176 ++++++++++++++++++
> .../pci/controller/dwc/pcie-designware-ep.c | 5 +
> .../pci/controller/dwc/pcie-designware-host.c | 6 +
> drivers/pci/controller/dwc/pcie-designware.c | 6 +
> drivers/pci/controller/dwc/pcie-designware.h | 21 +++
> include/linux/pcie-dwc.h | 2 +
> 9 files changed, 240 insertions(+)
> create mode 100644 Documentation/ABI/testing/debugfs-dwc-pcie
> create mode 100644 drivers/pci/controller/dwc/pcie-designware-debugfs.c
>

...

> +
> +static void dwc_pcie_rasdes_debugfs_deinit(struct dw_pcie *pci)
> +{
> + struct dwc_pcie_rasdes_info *rinfo = pci->debugfs->rasdes_info;
> +
> + mutex_destroy(&rinfo->reg_event_lock);
> +}
> +
> +static int dwc_pcie_rasdes_debugfs_init(struct dw_pcie *pci, struct dentry *dir)
> +{
> + struct dentry *rasdes_debug;
> + struct dwc_pcie_rasdes_info *rasdes_info;
> + struct device *dev = pci->dev;
> + int ras_cap;
> +
> + ras_cap = dw_pcie_find_rasdes_capability(pci);
> + if (!ras_cap) {
> + dev_dbg(dev, "no RASDES capability available\n");
> + return -ENODEV;
> + }
> +
> + rasdes_info = devm_kzalloc(dev, sizeof(*rasdes_info), GFP_KERNEL);
> + if (!rasdes_info)
> + return -ENOMEM;
> +
> + /* Create subdirectories for Debug, Error injection, Statistics */
> + rasdes_debug = debugfs_create_dir("rasdes_debug", dir);
> +
> + mutex_init(&rasdes_info->reg_event_lock);
> + rasdes_info->ras_cap_offset = ras_cap;
> + pci->debugfs->rasdes_info = rasdes_info;
> +
> + /* Create debugfs files for Debug subdirectory */
> + dwc_debugfs_create(lane_detect);
> + dwc_debugfs_create(rx_valid);
> +
> + return 0;
> +}
> +
> +void dwc_pcie_debugfs_deinit(struct dw_pcie *pci)
> +{
> + dwc_pcie_rasdes_debugfs_deinit(pci);
> + debugfs_remove_recursive(pci->debugfs->debug_dir);
> +}
> +
> +int dwc_pcie_debugfs_init(struct dw_pcie *pci)
> +{
> + char dirname[DWC_DEBUGFS_BUF_MAX];
> + struct device *dev = pci->dev;
> + struct debugfs_info *debugfs;
> + struct dentry *dir;
> + int ret;
> +
> + /* Create main directory for each platform driver */
> + snprintf(dirname, DWC_DEBUGFS_BUF_MAX, "dwc_pcie_%s", dev_name(dev));
> + dir = debugfs_create_dir(dirname, NULL);
> + debugfs = devm_kzalloc(dev, sizeof(*debugfs), GFP_KERNEL);
> + if (!debugfs)
> + return -ENOMEM;
> +
> + debugfs->debug_dir = dir;
> + pci->debugfs = debugfs;
> + ret = dwc_pcie_rasdes_debugfs_init(pci, dir);
> + if (ret)
> + dev_dbg(dev, "RASDES debugfs init failed\n");

What will happen if ret != 0? still return 0?

Fan
> +
> + return 0;
> +}
> diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
> index 72418160e658..f9d7f3f989ad 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-ep.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
> @@ -814,6 +814,7 @@ void dw_pcie_ep_cleanup(struct dw_pcie_ep *ep)
> {
> struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
>
> + dwc_pcie_debugfs_deinit(pci);
> dw_pcie_edma_remove(pci);
> }
> EXPORT_SYMBOL_GPL(dw_pcie_ep_cleanup);
> @@ -989,6 +990,10 @@ int dw_pcie_ep_init_registers(struct dw_pcie_ep *ep)
>
> dw_pcie_ep_init_non_sticky_registers(pci);
>
> + ret = dwc_pcie_debugfs_init(pci);
> + if (ret)
> + goto err_remove_edma;
> +
> return 0;
>
> err_remove_edma:
> diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
> index ffaded8f2df7..2081e8c72d12 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-host.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-host.c
> @@ -548,6 +548,10 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp)
> if (pp->ops->post_init)
> pp->ops->post_init(pp);
>
> + ret = dwc_pcie_debugfs_init(pci);
> + if (ret)
> + goto err_stop_link;
> +
> return 0;
>
> err_stop_link:
> @@ -572,6 +576,8 @@ void dw_pcie_host_deinit(struct dw_pcie_rp *pp)
> {
> struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>
> + dwc_pcie_debugfs_deinit(pci);
> +
> pci_stop_root_bus(pp->bridge->bus);
> pci_remove_root_bus(pp->bridge->bus);
>
> diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
> index a7c0671c6715..3d1d95d9e380 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.c
> +++ b/drivers/pci/controller/dwc/pcie-designware.c
> @@ -323,6 +323,12 @@ static u16 dw_pcie_find_vsec_capability(struct dw_pcie *pci,
> return 0;
> }
>
> +u16 dw_pcie_find_rasdes_capability(struct dw_pcie *pci)
> +{
> + return dw_pcie_find_vsec_capability(pci, dwc_pcie_rasdes_vsec_ids);
> +}
> +EXPORT_SYMBOL_GPL(dw_pcie_find_rasdes_capability);
> +
> int dw_pcie_read(void __iomem *addr, int size, u32 *val)
> {
> if (!IS_ALIGNED((uintptr_t)addr, size)) {
> diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
> index 501d9ddfea16..7f9807d4e5de 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.h
> +++ b/drivers/pci/controller/dwc/pcie-designware.h
> @@ -437,6 +437,11 @@ struct dw_pcie_ops {
> void (*stop_link)(struct dw_pcie *pcie);
> };
>
> +struct debugfs_info {
> + struct dentry *debug_dir;
> + void *rasdes_info;
> +};
> +
> struct dw_pcie {
> struct device *dev;
> void __iomem *dbi_base;
> @@ -465,6 +470,7 @@ struct dw_pcie {
> struct reset_control_bulk_data core_rsts[DW_PCIE_NUM_CORE_RSTS];
> struct gpio_desc *pe_rst;
> bool suspended;
> + struct debugfs_info *debugfs;
> };
>
> #define to_dw_pcie_from_pp(port) container_of((port), struct dw_pcie, pp)
> @@ -478,6 +484,7 @@ void dw_pcie_version_detect(struct dw_pcie *pci);
>
> u8 dw_pcie_find_capability(struct dw_pcie *pci, u8 cap);
> u16 dw_pcie_find_ext_capability(struct dw_pcie *pci, u8 cap);
> +u16 dw_pcie_find_rasdes_capability(struct dw_pcie *pci);
>
> int dw_pcie_read(void __iomem *addr, int size, u32 *val);
> int dw_pcie_write(void __iomem *addr, int size, u32 val);
> @@ -806,4 +813,18 @@ dw_pcie_ep_get_func_from_ep(struct dw_pcie_ep *ep, u8 func_no)
> return NULL;
> }
> #endif
> +
> +#ifdef CONFIG_PCIE_DW_DEBUGFS
> +int dwc_pcie_debugfs_init(struct dw_pcie *pci);
> +void dwc_pcie_debugfs_deinit(struct dw_pcie *pci);
> +#else
> +static inline int dwc_pcie_debugfs_init(struct dw_pcie *pci)
> +{
> + return 0;
> +}
> +static inline void dwc_pcie_debugfs_deinit(struct dw_pcie *pci)
> +{
> +}
> +#endif
> +
> #endif /* _PCIE_DESIGNWARE_H */
> diff --git a/include/linux/pcie-dwc.h b/include/linux/pcie-dwc.h
> index 40f3545731c8..6436e7fadc75 100644
> --- a/include/linux/pcie-dwc.h
> +++ b/include/linux/pcie-dwc.h
> @@ -28,6 +28,8 @@ static const struct dwc_pcie_vsec_id dwc_pcie_rasdes_vsec_ids[] = {
> .vsec_id = 0x02, .vsec_rev = 0x4 },
> { .vendor_id = PCI_VENDOR_ID_QCOM,
> .vsec_id = 0x02, .vsec_rev = 0x4 },
> + { .vendor_id = PCI_VENDOR_ID_SAMSUNG,
> + .vsec_id = 0x02, .vsec_rev = 0x4 },
> {} /* terminator */
> };
>
> --
> 2.17.1
>