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Wed, 05 Mar 2025 19:45:05 -0800 (PST) Date: Thu, 6 Mar 2025 09:14:59 +0530 From: Manivannan Sadhasivam To: Krishna Chaitanya Chundru Cc: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Helgaas , Jingoo Han , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, quic_mrana@quicinc.com, quic_vbadigan@quicinc.com Subject: Re: [PATCH v7 3/4] PCI: dwc: Improve handling of PCIe lane configuration Message-ID: <20250306034459.uc4qlnsnxijotplo@thinkpad> References: <20250225-preset_v6-v7-0-a593f3ef3951@oss.qualcomm.com> <20250225-preset_v6-v7-3-a593f3ef3951@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20250225-preset_v6-v7-3-a593f3ef3951@oss.qualcomm.com> On Tue, Feb 25, 2025 at 05:15:06PM +0530, Krishna Chaitanya Chundru wrote: > Currently even if the number of lanes hardware supports is equal to > the number lanes provided in the devicetree, the driver is trying to > configure again the maximum number of lanes which is not needed. > > Update number of lanes only when it is not equal to hardware capability. > 'Update max link width only...' > And also if the num-lanes property is not present in the devicetree > update the num_lanes with the maximum hardware supports. '...update 'pci->num_lanes' with the hardware supported maximum link width using the newly introduced dw_pcie_link_get_max_link_width() API.' > > Introduce dw_pcie_link_get_max_link_width() to get the maximum lane > width the hardware supports. > > Signed-off-by: Krishna Chaitanya Chundru > --- > drivers/pci/controller/dwc/pcie-designware-host.c | 3 +++ > drivers/pci/controller/dwc/pcie-designware.c | 11 ++++++++++- > drivers/pci/controller/dwc/pcie-designware.h | 1 + > 3 files changed, 14 insertions(+), 1 deletion(-) > > diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c > index ffaded8f2df7..dd56cc02f4ef 100644 > --- a/drivers/pci/controller/dwc/pcie-designware-host.c > +++ b/drivers/pci/controller/dwc/pcie-designware-host.c > @@ -504,6 +504,9 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) > > dw_pcie_iatu_detect(pci); > > + if (pci->num_lanes < 1) > + pci->num_lanes = dw_pcie_link_get_max_link_width(pci); > + > /* > * Allocate the resource for MSG TLP before programming the iATU > * outbound window in dw_pcie_setup_rc(). Since the allocation depends > diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c > index 145e7f579072..9fc5916867b6 100644 > --- a/drivers/pci/controller/dwc/pcie-designware.c > +++ b/drivers/pci/controller/dwc/pcie-designware.c > @@ -737,12 +737,21 @@ static void dw_pcie_link_set_max_speed(struct dw_pcie *pci) > > } > > +int dw_pcie_link_get_max_link_width(struct dw_pcie *pci) > +{ > + u8 cap = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); > + u32 lnkcap = dw_pcie_readl_dbi(pci, cap + PCI_EXP_LNKCAP); > + > + return FIELD_GET(PCI_EXP_LNKCAP_MLW, lnkcap); > +} > + > static void dw_pcie_link_set_max_link_width(struct dw_pcie *pci, u32 num_lanes) > { > + int max_lanes = dw_pcie_link_get_max_link_width(pci); > u32 lnkcap, lwsc, plc; > u8 cap; > > - if (!num_lanes) > + if (max_lanes == num_lanes) This gives the assumption that the link width in PCIE_PORT_LINK_CONTROL and PCIE_LINK_WIDTH_SPEED_CONTROL registers are same as MLW. Is it really true as per the DWC spec? - Mani -- மணிவண்ணன் சதாசிவம்