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[209.17.68.221]) by smtp.gmail.com with UTF8SMTPSA id 98e67ed59e1d1-301034433e9sm909027a91.1.2025.03.11.00.25.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Mar 2025 00:25:48 -0700 (PDT) Date: Tue, 11 Mar 2025 16:25:46 +0900 From: Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= To: Siddharth Vadapalli Cc: lpieralisi@kernel.org, vigneshr@ti.com, manivannan.sadhasivam@linaro.org, robh@kernel.org, bhelgaas@google.com, rogerq@kernel.org, linux-omap@vger.kernel.org, linux-pci@vger.kernel.org, stable@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, srk@ti.com Subject: Re: [PATCH] PCI: j721e: Fix the value of linkdown_irq_regfield for J784S4 Message-ID: <20250311072546.GA277060@rocinante> References: <20250305132018.2260771-1-s-vadapalli@ti.com> <20250310210746.GA2377483@rocinante> <20250311051806.smcu4o4dxpngimth@uda0492258> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250311051806.smcu4o4dxpngimth@uda0492258> Hello, > > > Hence, set 'linkdown_irq_regfield' to the macro 'J7200_LINK_DOWN' which > > > expands to BIT(10) and was first defined for the J7200 SoC. Other SoCs > > > already reuse this macro since it accurately represents the link-state > > > field in their respective "PCIE_INTD_ENABLE_REG_SYS_2" register. > > > > Can you confirm for me that the following use the correct macro? > > > > 333-static const struct j721e_pcie_data j721e_pcie_rc_data = { > > 337: .linkdown_irq_regfield = LINK_DOWN, > > > > 341-static const struct j721e_pcie_data j721e_pcie_ep_data = { > > 343: .linkdown_irq_regfield = LINK_DOWN, > > > > 347-static const struct j721e_pcie_data j7200_pcie_rc_data = { > > 350: .linkdown_irq_regfield = J7200_LINK_DOWN, > > > > 362-static const struct j721e_pcie_data am64_pcie_rc_data = { > > 364: .linkdown_irq_regfield = J7200_LINK_DOWN, > > > > 369-static const struct j721e_pcie_data am64_pcie_ep_data = { > > 371: .linkdown_irq_regfield = J7200_LINK_DOWN, > > > > 375-static const struct j721e_pcie_data j784s4_pcie_rc_data = { > > 379: .linkdown_irq_regfield = LINK_DOWN, > > > > 383-static const struct j721e_pcie_data j784s4_pcie_ep_data = { > > 385: .linkdown_irq_regfield = LINK_DOWN, > > > > 389-static const struct j721e_pcie_data j722s_pcie_rc_data = { > > 391: .linkdown_irq_regfield = J7200_LINK_DOWN, > > > > I am asking as some use LINK_DOWN, so I wanted to make sure. > > Yes, the above are accurate except for J784S4 which is fixed by this > patch. LINK_DOWN i.e. BIT(1) is applicable only to J721E which was the > first SoC after which the driver has been named. For all other SoCs, the > integration of the PCIe Controller into the SoC led to BIT(10) of the > register being used to indicate the link status. Sounds good! Thank you for letting me know. > > Tht said, the following has no .linkdown_irq_regfield property set: > > > > 355-static const struct j721e_pcie_data j7200_pcie_ep_data = { > > 356- .mode = PCI_MODE_EP, > > 357- .quirk_detect_quiet_flag = true, > > 358- .quirk_disable_flr = true, > > 359- .max_lanes = 2, > > 360-}; > > > > Would this be a problem? Or is this as expected? > > Thank you for pointing this out. This has to be fixed and the > "linkdown_irq_regfield" member has to be added to match > j7200_pcie_rc_data. I will post the fix for this. No need to send a new version. I will update the branch directly when I pull the patch. Not to worry. Thank you! Krzysztof