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[209.17.68.221]) by smtp.gmail.com with UTF8SMTPSA id d2e1a72fcca58-736e3f9d4f0sm3313957b3a.145.2025.03.11.08.00.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Mar 2025 08:00:01 -0700 (PDT) Date: Wed, 12 Mar 2025 00:00:00 +0900 From: Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= To: Siddharth Vadapalli Cc: lpieralisi@kernel.org, vigneshr@ti.com, manivannan.sadhasivam@linaro.org, robh@kernel.org, bhelgaas@google.com, rogerq@kernel.org, linux-omap@vger.kernel.org, linux-pci@vger.kernel.org, stable@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, srk@ti.com Subject: Re: [PATCH] PCI: j721e: Fix the value of linkdown_irq_regfield for J784S4 Message-ID: <20250311150000.GB1381004@rocinante> References: <20250305132018.2260771-1-s-vadapalli@ti.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250305132018.2260771-1-s-vadapalli@ti.com> Hello, > Commit under Fixes assigned the value of 'linkdown_irq_regfield' for the > J784S4 SoC as 'LINK_DOWN' which corresponds to BIT(1). However, according > to the Technical Reference Manual and Register Documentation for the J784S4 > SoC [0], BIT(1) corresponds to "ENABLE_SYS_EN_PCIE_DPA_1" which is __NOT__ > the field for the link-state interrupt. Instead, it is BIT(10) of the > "PCIE_INTD_ENABLE_REG_SYS_2" register that corresponds to the link-state > field named as "ENABLE_SYS_EN_PCIE_LINK_STATE". > > Hence, set 'linkdown_irq_regfield' to the macro 'J7200_LINK_DOWN' which > expands to BIT(10) and was first defined for the J7200 SoC. Other SoCs > already reuse this macro since it accurately represents the link-state > field in their respective "PCIE_INTD_ENABLE_REG_SYS_2" register. > > [0]: https://www.ti.com/lit/zip/spruj52 Applied to controller/j721e, thank you! Krzysztof