From: Bjorn Helgaas <helgaas@kernel.org>
To: "Luís Mendes" <luis.p.mendes@gmail.com>
Cc: "Marc Zyngier" <maz@kernel.org>, "Pali Rohár" <pali@kernel.org>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Thomas Petazzoni" <thomas.petazzoni@bootlin.com>,
"Lorenzo Pieralisi" <lorenzo.pieralisi@arm.com>,
"Rob Herring" <robh@kernel.org>,
"Krzysztof Wilczyński" <kw@linux.com>,
linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH] PCI: mvebu: Use devm_request_irq() for registering interrupt handler
Date: Tue, 11 Mar 2025 11:24:07 -0500 [thread overview]
Message-ID: <20250311162407.GA630741@bhelgaas> (raw)
In-Reply-To: <CAEzXK1qwHf5no6B2eCX1U7NGe-BoJYFLTHPkbM=_XpgrMAE2dw@mail.gmail.com>
On Sun, Mar 09, 2025 at 11:10:58PM +0000, Luís Mendes wrote:
> All logs presented were obtained from a SolidRun A388 ClearFog Base,
> if more detailed PCI logs are needed I have the other machine, the
> Armada Duo that has 2 PCIe slots and handles an AMD RX 550 GPU. Just
> let me know.
>
> - Complete dmesg log, booted with "pci=nomsi" is available here:
> https://pastebin.com/wDj0NGFN
> - Complete output of "sudo lspci -vv" is available here:
> https://pastebin.com/f4yHRhLr
> - Contents of /proc/interrupts is available here: https://pastebin.com/ejDUuhbJ
> - Output of "grep -r . /proc/irq/" is available here:
> https://pastebin.com/4jvFBBhy
Thank you very much for these.
It looks like the only PCI device is 01:00.0: [1ac1:089a], a Coral
Edge TPU, and I don't see any evidence of a driver for it or any IRQ
usage. Do you have any other PCI device you could try there?
Something with a driver that uses interrupts?
Not critical right now, but I'm puzzled by this part of the dmesg log:
mvebu-pcie soc:pcie: host bridge /soc/pcie ranges:
mvebu-pcie soc:pcie: MEM 0x00f1080000..0x00f1081fff -> 0x0000080000
mvebu-pcie soc:pcie: MEM 0x00f1040000..0x00f1041fff -> 0x0000040000
mvebu-pcie soc:pcie: MEM 0x00f1044000..0x00f1045fff -> 0x0000044000
mvebu-pcie soc:pcie: MEM 0x00f1048000..0x00f1049fff -> 0x0000048000
pci_bus 0000:00: root bus resource [mem 0xf1080000-0xf1081fff] (bus address [0x00080000-0x00081fff])
pci_bus 0000:00: root bus resource [mem 0xf1040000-0xf1041fff] (bus address [0x00040000-0x00041fff])
pci_bus 0000:00: root bus resource [mem 0xf1044000-0xf1045fff] (bus address [0x00044000-0x00045fff])
pci_bus 0000:00: root bus resource [mem 0xf1048000-0xf1049fff] (bus address [0x00048000-0x00049fff])
pci_bus 0000:00: root bus resource [mem 0xe0000000-0xe7ffffff]
The first four mvebu-pcie lines make good sense and match the
first four pci_bus lines. But I don't know where the
[mem 0xe0000000-0xe7ffffff] aperture came from. It should be
described in the devicetree, but I don't see it mentioned in the
/soc/pcie ranges.
Can you include the devicetree as well?
next prev parent reply other threads:[~2025-03-11 16:24 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-24 12:28 [PATCH] PCI: mvebu: Use devm_request_irq() for registering interrupt handler Pali Rohár
2022-06-23 13:10 ` Pali Rohár
2022-06-23 16:27 ` Bjorn Helgaas
2022-06-23 16:32 ` Pali Rohár
2022-06-23 16:49 ` Bjorn Helgaas
2022-06-23 20:31 ` Marc Zyngier
2025-02-26 21:50 ` Bjorn Helgaas
2025-03-01 19:49 ` Luís Mendes
2025-03-03 20:21 ` Bjorn Helgaas
2025-03-09 23:10 ` Luís Mendes
2025-03-11 16:24 ` Bjorn Helgaas [this message]
2025-03-12 16:25 ` Luís Mendes
2025-07-06 18:48 ` Luís Mendes
2022-07-01 14:29 ` Pali Rohár
2022-07-09 14:31 ` Pali Rohár
2022-07-09 23:44 ` Bjorn Helgaas
2022-07-10 0:06 ` Pali Rohár
2022-08-29 16:51 ` Pali Rohár
2022-09-11 15:45 ` Pali Rohár
2022-09-12 8:01 ` Lorenzo Pieralisi
2022-09-12 8:48 ` Pali Rohár
2022-09-12 8:55 ` Lorenzo Pieralisi
2022-09-12 9:03 ` Pali Rohár
2022-11-11 12:56 ` Lorenzo Pieralisi
2022-11-11 17:15 ` Pali Rohár
2022-11-14 9:33 ` Lorenzo Pieralisi
2022-11-06 23:25 ` Pali Rohár
2025-02-25 16:28 ` Bjorn Helgaas
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