Re: [PATCH 5/7] PCI: cadence: Update the PCIe controller register address offsets

[Bjorn Helgaas <helgaas@kernel.org>]

On Thu, Mar 27, 2025 at 11:41:36AM +0000, Manikandan Karunakaran Pillai wrote:
> Update the address offsets by removing the register bank offsets as
> register bank offset will be passed to the read and write functions

Add period at end of sentence.

> -#define CDNS_PCIE_HPA_LM_EP_FUNC_CFG		0x02c0
> +#define CDNS_PCIE_HPA_LM_EP_FUNC_CFG		(CDNS_PCIE_HPA_IP_REG_BANK + 0x02c0)

Pick either upper- or lowercase hex and use it consistently.  Most of
this patch uses uppercase.

>  static inline u32 cdns_reg_bank_to_off(struct cdns_pcie *pcie, enum cdns_pcie_reg_bank bank)
>  {
> -	u32 offset;
> +	u32 offset = 0x0;

No apparent reason for this initialization, since this doesn't change
the rest of the function.  Either the lack of initialization was a
defect and this should be split out to a bug fix patch, or it's not
needed at all.

>  	switch (bank) {
>  	case REG_BANK_IP_REG:
> @@ -668,7 +682,6 @@ static inline u32 cdns_reg_bank_to_off(struct cdns_pcie *pcie, enum cdns_pcie_re
>  	};
>  	return offset;
>  }
> -

Superfluous change, omit.

>  /* Register access */
>  static inline void cdns_pcie_writel(struct cdns_pcie *pcie, u32 reg, u32 value)
>  {