From: Niklas Cassel <cassel@kernel.org>
To: "Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Krzysztof Wilczyński" <kw@linux.com>,
"Manivannan Sadhasivam" <manivannan.sadhasivam@linaro.org>,
"Rob Herring" <robh@kernel.org>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Jingoo Han" <jingoohan1@gmail.com>,
"Kishon Vijay Abraham I" <kishon@kernel.org>
Cc: Wilfred Mallawa <wilfred.mallawa@wdc.com>,
Damien Le Moal <dlemoal@kernel.org>,
Niklas Cassel <cassel@kernel.org>,
stable+noautosel@kernel.org, linux-pci@vger.kernel.org
Subject: [PATCH v2 6/6] PCI: endpoint: cleanup set_msix() callback
Date: Tue, 13 May 2025 09:31:01 +0200 [thread overview]
Message-ID: <20250513073055.169486-14-cassel@kernel.org> (raw)
In-Reply-To: <20250513073055.169486-8-cassel@kernel.org>
The kdoc for pci_epc_set_msix() says:
"Invoke to set the required number of MSI-X interrupts."
the kdoc for the callback pci_epc_ops->set_msix() says:
"ops to set the requested number of MSI-X interrupts in the MSI-X
capability register"
pci_epc_ops->set_msix() does however expect the parameter 'interrupts' to
be in the encoding as defined by the Table Size field.
Nowhere in the kdoc does it say that the number of interrupts should be
in Table Size encoding.
Thus, it is very confusing that the wrapper function (pci_epc_set_msix())
and the callback function (pci_epc_ops->set_msix()) both take a parameter
named interrupts, but they both expect completely different encodings.
Cleanup the API so that the wrapper function and the callback function
will have the same semantics.
Cc: <stable+noautosel@kernel.org> # this is simply a cleanup
Signed-off-by: Niklas Cassel <cassel@kernel.org>
---
drivers/pci/controller/cadence/pcie-cadence-ep.c | 5 ++---
drivers/pci/controller/dwc/pcie-designware-ep.c | 5 ++---
drivers/pci/endpoint/pci-epc-core.c | 2 +-
3 files changed, 5 insertions(+), 7 deletions(-)
diff --git a/drivers/pci/controller/cadence/pcie-cadence-ep.c b/drivers/pci/controller/cadence/pcie-cadence-ep.c
index bbb310135977..542533a8c56a 100644
--- a/drivers/pci/controller/cadence/pcie-cadence-ep.c
+++ b/drivers/pci/controller/cadence/pcie-cadence-ep.c
@@ -294,14 +294,13 @@ static int cdns_pcie_ep_set_msix(struct pci_epc *epc, u8 fn, u8 vfn,
struct cdns_pcie *pcie = &ep->pcie;
u32 cap = CDNS_PCIE_EP_FUNC_MSIX_CAP_OFFSET;
u32 val, reg;
- u16 actual_interrupts = interrupts + 1;
fn = cdns_pcie_get_fn_from_vfn(pcie, fn, vfn);
reg = cap + PCI_MSIX_FLAGS;
val = cdns_pcie_ep_fn_readw(pcie, fn, reg);
val &= ~PCI_MSIX_FLAGS_QSIZE;
- val |= interrupts; /* 0's based value */
+ val |= interrupts - 1; /* encoded as N-1 */
cdns_pcie_ep_fn_writew(pcie, fn, reg, val);
/* Set MSI-X BAR and offset */
@@ -311,7 +310,7 @@ static int cdns_pcie_ep_set_msix(struct pci_epc *epc, u8 fn, u8 vfn,
/* Set PBA BAR and offset. BAR must match MSI-X BAR */
reg = cap + PCI_MSIX_PBA;
- val = (offset + (actual_interrupts * PCI_MSIX_ENTRY_SIZE)) | bir;
+ val = (offset + (interrupts * PCI_MSIX_ENTRY_SIZE)) | bir;
cdns_pcie_ep_fn_writel(pcie, fn, reg, val);
return 0;
diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
index d74d21c42559..0d204149a6e2 100644
--- a/drivers/pci/controller/dwc/pcie-designware-ep.c
+++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
@@ -586,7 +586,6 @@ static int dw_pcie_ep_set_msix(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
struct dw_pcie_ep_func *ep_func;
u32 val, reg;
- u16 actual_interrupts = interrupts + 1;
ep_func = dw_pcie_ep_get_func_from_ep(ep, func_no);
if (!ep_func || !ep_func->msix_cap)
@@ -597,7 +596,7 @@ static int dw_pcie_ep_set_msix(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
reg = ep_func->msix_cap + PCI_MSIX_FLAGS;
val = dw_pcie_ep_readw_dbi(ep, func_no, reg);
val &= ~PCI_MSIX_FLAGS_QSIZE;
- val |= interrupts; /* 0's based value */
+ val |= interrupts - 1; /* encoded as N-1 */
dw_pcie_writew_dbi(pci, reg, val);
reg = ep_func->msix_cap + PCI_MSIX_TABLE;
@@ -605,7 +604,7 @@ static int dw_pcie_ep_set_msix(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
dw_pcie_ep_writel_dbi(ep, func_no, reg, val);
reg = ep_func->msix_cap + PCI_MSIX_PBA;
- val = (offset + (actual_interrupts * PCI_MSIX_ENTRY_SIZE)) | bir;
+ val = (offset + (interrupts * PCI_MSIX_ENTRY_SIZE)) | bir;
dw_pcie_ep_writel_dbi(ep, func_no, reg, val);
dw_pcie_dbi_ro_wr_dis(pci);
diff --git a/drivers/pci/endpoint/pci-epc-core.c b/drivers/pci/endpoint/pci-epc-core.c
index 7b4a9292f801..ea4e64249949 100644
--- a/drivers/pci/endpoint/pci-epc-core.c
+++ b/drivers/pci/endpoint/pci-epc-core.c
@@ -382,7 +382,7 @@ int pci_epc_set_msix(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
return 0;
mutex_lock(&epc->lock);
- ret = epc->ops->set_msix(epc, func_no, vfunc_no, interrupts - 1, bir,
+ ret = epc->ops->set_msix(epc, func_no, vfunc_no, interrupts, bir,
offset);
mutex_unlock(&epc->lock);
--
2.49.0
next prev parent reply other threads:[~2025-05-13 7:31 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-13 7:30 [PATCH v2 0/6] PCI: endpoint: IRQ callback fixes and cleanups Niklas Cassel
2025-05-13 7:30 ` [PATCH v2 1/6] PCI: dwc: ep: Fix broken set_msix() callback Niklas Cassel
2025-05-13 7:30 ` [PATCH v2 2/6] PCI: cadence-ep: " Niklas Cassel
2025-05-13 7:30 ` [PATCH v2 3/6] PCI: endpoint: cleanup get_msi() callback Niklas Cassel
2025-05-14 6:35 ` Damien Le Moal
2025-05-13 7:30 ` [PATCH v2 4/6] PCI: endpoint: cleanup set_msi() callback Niklas Cassel
2025-05-14 6:39 ` Damien Le Moal
2025-05-13 7:31 ` [PATCH v2 5/6] PCI: endpoint: cleanup get_msix() callback Niklas Cassel
2025-05-14 6:41 ` Damien Le Moal
2025-05-13 7:31 ` Niklas Cassel [this message]
2025-05-14 6:43 ` [PATCH v2 6/6] PCI: endpoint: cleanup set_msix() callback Damien Le Moal
2025-05-13 10:25 ` [PATCH v2 0/6] PCI: endpoint: IRQ callback fixes and cleanups Krzysztof Wilczyński
2025-05-13 12:31 ` Niklas Cassel
2025-05-13 16:03 ` Manivannan Sadhasivam
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