From: Greg KH <gregkh@linuxfoundation.org>
To: "Macpaul Lin (林智斌)" <Macpaul.Lin@mediatek.com>
Cc: "Deren Wu (武德仁)" <Deren.Wu@mediatek.com>,
"Johnny-CC Chang (張晋嘉)" <Johnny-CC.Chang@mediatek.com>,
"Mingyen Hsieh (謝明諺)" <Mingyen.Hsieh@mediatek.com>,
"Yenchia Chen (陳彥嘉)" <Yenchia.Chen@mediatek.com>,
"Pablo Sun (孫毓翔)" <pablo.sun@mediatek.com>,
"helgaas@kernel.org" <helgaas@kernel.org>,
"Jieyy Yang (杨洁)" <Jieyy.Yang@mediatek.com>,
"ajayagarwal@google.com" <ajayagarwal@google.com>,
"sashal@kernel.org" <sashal@kernel.org>,
"linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
"Bear Wang (萩原惟德)" <bear.wang@mediatek.com>,
"david.e.box@linux.intel.com" <david.e.box@linux.intel.com>,
"johan+linaro@kernel.org" <johan+linaro@kernel.org>,
"ilpo.jarvinen@linux.intel.com" <ilpo.jarvinen@linux.intel.com>,
"sdalvi@google.com" <sdalvi@google.com>,
"manivannan.sadhasivam@linaro.org"
<manivannan.sadhasivam@linaro.org>,
"Hanson Lin (林聖峰)" <Hanson.Lin@mediatek.com>,
"hkallweit1@gmail.com" <hkallweit1@gmail.com>,
"xueshuai@linux.alibaba.com" <xueshuai@linux.alibaba.com>,
"manugautam@google.com" <manugautam@google.com>,
"stable@vger.kernel.org" <stable@vger.kernel.org>,
"bhelgaas@google.com" <bhelgaas@google.com>,
"vidyas@nvidia.com" <vidyas@nvidia.com>
Subject: Re: [PATCH v3] PCI/ASPM: Disable L1 before disabling L1ss
Date: Thu, 5 Jun 2025 13:27:04 +0200 [thread overview]
Message-ID: <2025060543-arrest-facecloth-89e6@gregkh> (raw)
In-Reply-To: <8a7897f69c6347833c8e37ca5991ab051933de6e.camel@mediatek.com>
On Thu, Jun 05, 2025 at 11:23:02AM +0000, Macpaul Lin (林智斌) wrote:
> On Tue, 2024-10-22 at 17:30 -0500, Bjorn Helgaas wrote:
> > On Mon, Oct 07, 2024 at 08:59:17AM +0530, Ajay Agarwal wrote:
> > > The current sequence in the driver for L1ss update is as follows.
> > >
> > > Disable L1ss
> > > Disable L1
> > > Enable L1ss as required
> > > Enable L1 if required
> > >
> > > With this sequence, a bus hang is observed during the L1ss
> > > disable sequence when the RC CPU attempts to clear the RC L1ss
> > > register after clearing the EP L1ss register. It looks like the
> > > RC attempts to enter L1ss again and at the same time, access to
> > > RC L1ss register fails because aux clk is still not active.
> > >
> > > PCIe spec r6.2, section 5.5.4, recommends that setting either
> > > or both of the enable bits for ASPM L1 PM Substates must be done
> > > while ASPM L1 is disabled. My interpretation here is that
> > > clearing L1ss should also be done when L1 is disabled. Thereby,
> > > change the sequence as follows.
> > >
> > > Disable L1
> > > Disable L1ss
> > > Enable L1ss as required
> > > Enable L1 if required
> > >
> > > Signed-off-by: Ajay Agarwal <ajayagarwal@google.com>
> >
> > Applied to pci/aspm for v6.13, thank you, Ajay!
>
> Thanks! MediaTek also found this issue will happen on some old kernel,
> for example 6.11 or 6.12. would you please pick this patch also to some
> stable tree?
>
> LINK:https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/drivers/pci/pcie/aspm.c?id=7447990137bf06b2aeecad9c6081e01a9f47f2aa
Please submit it properly, with your signed-off-by and we will be glad
to consider it.
thanks,
greg k-h
prev parent reply other threads:[~2025-06-05 11:27 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-07 3:29 [PATCH v3] PCI/ASPM: Disable L1 before disabling L1ss Ajay Agarwal
2024-10-18 15:25 ` Ajay Agarwal
2024-10-22 22:30 ` Bjorn Helgaas
2025-06-05 11:23 ` Macpaul Lin (林智斌)
2025-06-05 11:27 ` Greg KH [this message]
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