From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7E9542DECDD; Thu, 12 Jun 2025 21:26:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749763574; cv=none; b=oT9l+1KjcpiHrJStexK2Uyj7bgIJ33TfKMOD4dI41Wy86hPJpzgK0xd3KRnUSt/v+smThvAai3IflCObODOKeDtIhxAhNp+jvdjyXITUTgGhiGgWm0n0GF4sxQIIcnEqXeLaqrO25+xh/7mSX3yxg8lRlCjyHI+rujABc7suA1g= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749763574; c=relaxed/simple; bh=6LN6fAd/m/I9fNEg7TgOenHz2E9XCA7dKBTgHZOBjA8=; h=Date:From:To:Cc:Subject:Message-ID:MIME-Version:Content-Type: Content-Disposition:In-Reply-To; b=OexydmSrLlVsIn6YwIEU661YKnUhS+WQskZCtLqtq+YuHy1B90aDuKltMH3Hxa1uxAoBJxATBa3/0J8MQSQN0WlZ42nERLinb4n1oVbZxmoE5QZo9Pjz8l14n9r4hpERrtON14Pk9+28KcIkSRhK0ZD8XIS+rJm1pK31COB9Htw= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=RBaMKN7q; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="RBaMKN7q" Received: by smtp.kernel.org (Postfix) with ESMTPSA id CC57BC4CEEA; Thu, 12 Jun 2025 21:26:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1749763574; bh=6LN6fAd/m/I9fNEg7TgOenHz2E9XCA7dKBTgHZOBjA8=; h=Date:From:To:Cc:Subject:In-Reply-To:From; b=RBaMKN7q88dt2SCpxiQd0GEzWLoqZ3LCGCt9XYhCziHo3YTanavefSp3NTXwZoNYZ m5de7yzQyI5k/vHv0PIBgllwvEpY/fsvmLgb0AI2ad+czensyPXFO8i1hT9JU3/cbT X0zRj+iLUNTXEdGCgdRoW8aOo9FEx4b6KOZ9C1/WB92PFTWmrHWM04U3uBbibYYaUF OY2LHGIBxnedMxi7F6cIK5ENto+BNsECzamLjIMVFZ/NSxxkHVkxUvQ2hKa4bvIWOC lMQQ/y+Wu7gJgliZ7GfR2Z/cn7/rKnKvapr87pGvvL2zEw9078jcOjvCWL2meKHGrG 4T3R31JTy0F8A== Date: Thu, 12 Jun 2025 16:26:12 -0500 From: Bjorn Helgaas To: Geraldo Nascimento Cc: linux-rockchip@lists.infradead.org, Shawn Lin , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Heiko Stuebner , Vinod Koul , Kishon Vijay Abraham I , linux-phy@lists.infradead.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [RFC PATCH v2 1/4] PCI: pcie-rockchip: add Link Control and Status Register 2 Message-ID: <20250612212612.GA930681@bhelgaas> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: On Thu, Jun 12, 2025 at 05:49:57PM -0300, Geraldo Nascimento wrote: > On Wed, Jun 11, 2025 at 02:42:59PM -0500, Bjorn Helgaas wrote: > > I would do a pure conversion patch of the existing #defines. Then I > > suspect you wouldn't need a patch to add the Link 2 registers at all > > because you could just use the #defines from pci_regs.h. > > Hi Bjorn, > > I've hit roadblock, maybe you can help? > > PCIE_RC_CONFIG_DCR_CSPL_LIMIT is defined as 0xff... > > I'd like to kill that define too, since it will be > orphaned. > > But hardcoding 0xff seems like illegible solution. > > Perhaps there is another standard define that > maps to 0xff that I can use? Anyone comes > to your mind? Maybe FIELD_MAX(PCI_EXP_DEVCAP_PWR_VAL)?