From: Jacky Chou <jacky_chou@aspeedtech.com>
To: <bhelgaas@google.com>, <lpieralisi@kernel.org>,
<kwilczynski@kernel.org>, <mani@kernel.org>, <robh@kernel.org>,
<krzk+dt@kernel.org>, <conor+dt@kernel.org>, <joel@jms.id.au>,
<andrew@codeconstruct.com.au>, <vkoul@kernel.org>,
<kishon@kernel.org>, <linus.walleij@linaro.org>,
<p.zabel@pengutronix.de>, <linux-aspeed@lists.ozlabs.org>,
<linux-pci@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>, <linux-phy@lists.infradead.org>,
<openbmc@lists.ozlabs.org>, <linux-gpio@vger.kernel.org>
Cc: <elbadrym@google.com>, <romlem@google.com>, <anhphan@google.com>,
<wak@google.com>, <yuxiaozhang@google.com>,
<BMC-SW@aspeedtech.com>
Subject: [PATCH 5/7] ARM: dts: aspeed-g6: Add PCIe RC node
Date: Fri, 13 Jun 2025 11:29:59 +0800 [thread overview]
Message-ID: <20250613033001.3153637-6-jacky_chou@aspeedtech.com> (raw)
In-Reply-To: <20250613033001.3153637-1-jacky_chou@aspeedtech.com>
The AST2600 has one PCIe RC, and add the relative configure regmap.
Signed-off-by: Jacky Chou <jacky_chou@aspeedtech.com>
---
arch/arm/boot/dts/aspeed/aspeed-g6.dtsi | 53 +++++++++++++++++++++++++
1 file changed, 53 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi
index 8ed715bd53aa..d46a151e3c99 100644
--- a/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi
+++ b/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi
@@ -379,6 +379,59 @@ rng: hwrng@1e6e2524 {
quality = <100>;
};
+ pcie_phy1: pcie-phy@1e6ed200 {
+ compatible = "aspeed,ast2600-pcie-phy", "syscon";
+ reg = <0x1e6ed200 0x100>;
+ };
+
+ pcie_cfg: pcie-cfg@1e770000 {
+ compatible = "aspeed,ast2600-pcie-cfg", "syscon";
+ reg = <0x1e770000 0x80>;
+ };
+
+ pcie0: pcie@1e7700c0 {
+ compatible = "aspeed,ast2600-pcie";
+ device_type = "pci";
+ reg = <0x1e7700c0 0x40>;
+ linux,pci-domain = <0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
+ bus-range = <0x80 0xff>;
+
+ ranges = <0x01000000 0x0 0x00018000 0x00018000 0x0 0x00008000
+ 0x02000000 0x0 0x70000000 0x70000000 0x0 0x10000000>;
+
+ status = "disabled";
+
+ resets = <&syscon ASPEED_RESET_H2X>,
+ <&syscon ASPEED_RESET_PCIE_RC_O>;
+ reset-names = "h2x", "perst";
+ clocks = <&syscon ASPEED_CLK_GATE_BCLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pcierc1_default>;
+
+ #interrupt-cells = <1>;
+ msi-parent = <&pcie0>;
+ msi-controller;
+ msi_address = <0x1e77005c>;
+
+ aspeed,ahbc = <&ahbc>;
+ aspeed,pciecfg = <&pcie_cfg>;
+ aspeed,pciephy = <&pcie_phy1>;
+
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie_intc0 0>,
+ <0 0 0 2 &pcie_intc0 1>,
+ <0 0 0 3 &pcie_intc0 2>,
+ <0 0 0 4 &pcie_intc0 3>;
+ pcie_intc0: interrupt-controller {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ };
+ };
+
gfx: display@1e6e6000 {
compatible = "aspeed,ast2600-gfx", "syscon";
reg = <0x1e6e6000 0x1000>;
--
2.43.0
next prev parent reply other threads:[~2025-06-13 3:30 UTC|newest]
Thread overview: 49+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-13 3:29 [PATCH 0/7] Add ASPEED PCIe Root Complex support Jacky Chou
2025-06-13 3:29 ` [PATCH 1/7] dt-bindings: phy: Add document for ASPEED PCIe PHY Jacky Chou
2025-06-13 9:14 ` neil.armstrong
2025-06-20 5:03 ` 回覆: " Jacky Chou
2025-06-13 9:44 ` Krzysztof Kozlowski
2025-06-20 8:29 ` 回覆: " Jacky Chou
2025-06-13 3:29 ` [PATCH 2/7] dt-bindings: pci: Add document for ASPEED PCIe Config Jacky Chou
2025-06-13 9:46 ` Krzysztof Kozlowski
2025-06-20 8:32 ` 回覆: " Jacky Chou
2025-06-13 15:58 ` Bjorn Helgaas
2025-06-20 5:27 ` Jacky Chou
2025-06-13 3:29 ` [PATCH 3/7] dt-bindings: pci: Add document for ASPEED PCIe RC Jacky Chou
2025-06-13 9:50 ` Krzysztof Kozlowski
2025-06-20 8:36 ` Jacky Chou
2025-06-25 21:04 ` Rob Herring
2025-06-27 9:59 ` 回覆: " Jacky Chou
2025-06-13 3:29 ` [PATCH 4/7] ARM: dts: aspeed-g6: Add AST2600 PCIe RC PERST ctrl pin Jacky Chou
2025-06-13 9:51 ` Krzysztof Kozlowski
2025-06-20 8:36 ` Jacky Chou
2025-06-13 15:59 ` Bjorn Helgaas
2025-06-13 3:29 ` Jacky Chou [this message]
2025-06-13 15:54 ` [PATCH 5/7] ARM: dts: aspeed-g6: Add PCIe RC node Bjorn Helgaas
2025-06-20 5:24 ` 回覆: " Jacky Chou
2025-06-24 15:28 ` Bjorn Helgaas
2025-06-25 8:27 ` 回覆: " Jacky Chou
2025-06-25 22:16 ` Bjorn Helgaas
2025-06-27 10:02 ` Jacky Chou
2025-06-13 3:30 ` [PATCH 6/7] pinctrl: aspeed-g6: Add PCIe RC PERST pin group Jacky Chou
2025-06-18 12:15 ` Linus Walleij
2025-06-20 7:09 ` Andrew Jeffery
2025-06-13 3:30 ` [PATCH 7/7] pci: aspeed: Add ASPEED PCIe host controller driver Jacky Chou
2025-06-13 9:54 ` Krzysztof Kozlowski
2025-06-23 2:42 ` 回覆: " Jacky Chou
2025-06-13 12:03 ` Ilpo Järvinen
2025-06-23 5:41 ` Jacky Chou
2025-06-24 10:50 ` Ilpo Järvinen
2025-06-24 11:11 ` 回覆: " Jacky Chou
2025-06-24 15:40 ` Bjorn Helgaas
2025-06-25 8:32 ` 回覆: " Jacky Chou
2025-06-13 16:28 ` Bjorn Helgaas
2025-06-20 6:05 ` 回覆: " Jacky Chou
2025-06-24 15:33 ` Bjorn Helgaas
2025-06-14 2:07 ` kernel test robot
2025-06-19 8:14 ` kernel test robot
2025-06-13 9:18 ` [PATCH 0/7] Add ASPEED PCIe Root Complex support neil.armstrong
2025-06-20 8:20 ` 回覆: " Jacky Chou
2025-06-24 7:29 ` Neil Armstrong
2025-06-24 10:54 ` 回覆: " Jacky Chou
2025-06-16 21:46 ` Rob Herring (Arm)
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