From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0D39B28640F; Wed, 18 Jun 2025 10:19:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750241954; cv=none; b=fldKnv/F/MZH0mszybr56phQvDRSqjWFgkj59P6j4X8t3oK17nXNK2MMhlJmwixwICXo7fSkjOCgPHWEUxfRUUR+dSy8ayqSQ0aL0CRKN35AaFU1KpR+7tJg4ZUIg07CoTyYU2pNfF5CmofNmea0PMaLSzvmvYSeRwV3fc1FH0A= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750241954; c=relaxed/simple; bh=cMjcYS3nYWnZwMk3IuZcL+D8usjwsSZbBSXX5Y6yRtU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=JpqMC7dRX7cKq+J10gTo6XPUfLyV/m/ieZbSQNXx5pnVfduLkL5OKKCfRtTsvQSLxUDoQwC8/V6ihQwG1klUxOkGdQFik7goJkHA1Q7fknwlqwgtAcTemb2HhfkHwOmQzt6DNMshVVxSa9bNYZaoobmF2QBEIxCMe+xA+QcKFBA= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=i6wKPjQp; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="i6wKPjQp" Received: by smtp.kernel.org (Postfix) with ESMTPSA id A32ECC4CEE7; Wed, 18 Jun 2025 10:19:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1750241953; bh=cMjcYS3nYWnZwMk3IuZcL+D8usjwsSZbBSXX5Y6yRtU=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=i6wKPjQp+prz+15NPaOgNmPqfGAHBHDh4fZv1CGPy6gn303Bmp/cchlDR/dvVNmQK xz0fvEDTCf+IXpv5t9+0K5rrPnYBQV9GWPnf7q09htC8k+D3jps2zGFcuGo3spCYXJ ENupCQlH5zGGzlJ9+PzKl7mJjvTHwhTAiwA3/s3IbyqH8DJgbK8tQjMni+NDPwazzB 9EKRVOrfZolHvlcrYgWqYD4OzNV5p6GfrxdNIBZ8I0HCCSug/k1bBTh7DQgmzY1dTv c2XSHReAN9597rAqgIRePuTg2P5Wn10+NciqUKX2ULBhXkLEg6c/gAIaU/iWUQag1M ttyL5YMB5rVQQ== From: Lorenzo Pieralisi Date: Wed, 18 Jun 2025 12:17:31 +0200 Subject: [PATCH v5 16/27] arm64: cpucaps: Rename GICv3 CPU interface capability Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20250618-gicv5-host-v5-16-d9e622ac5539@kernel.org> References: <20250618-gicv5-host-v5-0-d9e622ac5539@kernel.org> In-Reply-To: <20250618-gicv5-host-v5-0-d9e622ac5539@kernel.org> To: Marc Zyngier , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Will Deacon Cc: Arnd Bergmann , Sascha Bischoff , Jonathan Cameron , Timothy Hayes , Bjorn Helgaas , "Liam R. Howlett" , Peter Maydell , Mark Rutland , Jiri Slaby , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-pci@vger.kernel.org, Lorenzo Pieralisi X-Mailer: b4 0.15-dev-6f78e In preparation for adding a GICv5 CPU interface capability, rework the existing GICv3 CPUIF capability - change its name and description so that the subsequent GICv5 CPUIF capability can be added with a more consistent naming on top. Suggested-by: Mark Rutland Signed-off-by: Lorenzo Pieralisi Cc: Will Deacon Cc: Catalin Marinas Cc: Marc Zyngier --- arch/arm64/kernel/cpufeature.c | 10 +++++----- arch/arm64/tools/cpucaps | 2 +- drivers/irqchip/irq-gic.c | 2 +- 3 files changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index b34044e20128..42ba76b6c8cd 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -2296,11 +2296,11 @@ static bool can_use_gic_priorities(const struct arm64_cpu_capabilities *entry, int scope) { /* - * ARM64_HAS_GIC_CPUIF_SYSREGS has a lower index, and is a boot CPU + * ARM64_HAS_GICV3_CPUIF has a lower index, and is a boot CPU * feature, so will be detected earlier. */ - BUILD_BUG_ON(ARM64_HAS_GIC_PRIO_MASKING <= ARM64_HAS_GIC_CPUIF_SYSREGS); - if (!cpus_have_cap(ARM64_HAS_GIC_CPUIF_SYSREGS)) + BUILD_BUG_ON(ARM64_HAS_GIC_PRIO_MASKING <= ARM64_HAS_GICV3_CPUIF); + if (!cpus_have_cap(ARM64_HAS_GICV3_CPUIF)) return false; return enable_pseudo_nmi; @@ -2496,8 +2496,8 @@ static const struct arm64_cpu_capabilities arm64_features[] = { .matches = has_always, }, { - .desc = "GIC system register CPU interface", - .capability = ARM64_HAS_GIC_CPUIF_SYSREGS, + .desc = "GICv3 CPU interface", + .capability = ARM64_HAS_GICV3_CPUIF, .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, .matches = has_useable_gicv3_cpuif, ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, GIC, IMP) diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps index 10effd4cff6b..a7a4d9e6e12e 100644 --- a/arch/arm64/tools/cpucaps +++ b/arch/arm64/tools/cpucaps @@ -35,7 +35,7 @@ HAS_GENERIC_AUTH HAS_GENERIC_AUTH_ARCH_QARMA3 HAS_GENERIC_AUTH_ARCH_QARMA5 HAS_GENERIC_AUTH_IMP_DEF -HAS_GIC_CPUIF_SYSREGS +HAS_GICV3_CPUIF HAS_GIC_PRIO_MASKING HAS_GIC_PRIO_RELAXED_SYNC HAS_HCR_NV1 diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c index 6503573557fd..1269ab8eb726 100644 --- a/drivers/irqchip/irq-gic.c +++ b/drivers/irqchip/irq-gic.c @@ -54,7 +54,7 @@ static void gic_check_cpu_features(void) { - WARN_TAINT_ONCE(this_cpu_has_cap(ARM64_HAS_GIC_CPUIF_SYSREGS), + WARN_TAINT_ONCE(this_cpu_has_cap(ARM64_HAS_GICV3_CPUIF), TAINT_CPU_OUT_OF_SPEC, "GICv3 system registers enabled, broken firmware!\n"); } -- 2.48.0