From: Lorenzo Pieralisi <lpieralisi@kernel.org>
To: Marc Zyngier <maz@kernel.org>,
Thomas Gleixner <tglx@linutronix.de>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will@kernel.org>
Cc: Arnd Bergmann <arnd@arndb.de>,
Sascha Bischoff <sascha.bischoff@arm.com>,
Jonathan Cameron <Jonathan.Cameron@huawei.com>,
Timothy Hayes <timothy.hayes@arm.com>,
Bjorn Helgaas <bhelgaas@google.com>,
"Liam R. Howlett" <Liam.Howlett@oracle.com>,
Peter Maydell <peter.maydell@linaro.org>,
Mark Rutland <mark.rutland@arm.com>,
Jiri Slaby <jirislaby@kernel.org>,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
linux-pci@vger.kernel.org,
Lorenzo Pieralisi <lpieralisi@kernel.org>
Subject: [PATCH v5 06/27] arm64/sysreg: Add ICC_PPI_ENABLER<n>_EL1
Date: Wed, 18 Jun 2025 12:17:21 +0200 [thread overview]
Message-ID: <20250618-gicv5-host-v5-6-d9e622ac5539@kernel.org> (raw)
In-Reply-To: <20250618-gicv5-host-v5-0-d9e622ac5539@kernel.org>
Add ICC_PPI_ENABLER<n>_EL1 registers sysreg description.
Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Will Deacon <will@kernel.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Marc Zyngier <maz@kernel.org>
---
arch/arm64/tools/sysreg | 75 +++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 75 insertions(+)
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index 7f096efee4e7..728223df482d 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -3113,6 +3113,81 @@ Field 1 Enabled
Field 0 F
EndSysreg
+SysregFields ICC_PPI_ENABLERx_EL1
+Field 63 EN63
+Field 62 EN62
+Field 61 EN61
+Field 60 EN60
+Field 59 EN59
+Field 58 EN58
+Field 57 EN57
+Field 56 EN56
+Field 55 EN55
+Field 54 EN54
+Field 53 EN53
+Field 52 EN52
+Field 51 EN51
+Field 50 EN50
+Field 49 EN49
+Field 48 EN48
+Field 47 EN47
+Field 46 EN46
+Field 45 EN45
+Field 44 EN44
+Field 43 EN43
+Field 42 EN42
+Field 41 EN41
+Field 40 EN40
+Field 39 EN39
+Field 38 EN38
+Field 37 EN37
+Field 36 EN36
+Field 35 EN35
+Field 34 EN34
+Field 33 EN33
+Field 32 EN32
+Field 31 EN31
+Field 30 EN30
+Field 29 EN29
+Field 28 EN28
+Field 27 EN27
+Field 26 EN26
+Field 25 EN25
+Field 24 EN24
+Field 23 EN23
+Field 22 EN22
+Field 21 EN21
+Field 20 EN20
+Field 19 EN19
+Field 18 EN18
+Field 17 EN17
+Field 16 EN16
+Field 15 EN15
+Field 14 EN14
+Field 13 EN13
+Field 12 EN12
+Field 11 EN11
+Field 10 EN10
+Field 9 EN9
+Field 8 EN8
+Field 7 EN7
+Field 6 EN6
+Field 5 EN5
+Field 4 EN4
+Field 3 EN3
+Field 2 EN2
+Field 1 EN1
+Field 0 EN0
+EndSysregFields
+
+Sysreg ICC_PPI_ENABLER0_EL1 3 0 12 10 6
+Fields ICC_PPI_ENABLERx_EL1
+EndSysreg
+
+Sysreg ICC_PPI_ENABLER1_EL1 3 0 12 10 7
+Fields ICC_PPI_ENABLERx_EL1
+EndSysreg
+
SysregFields ICC_PPI_PRIORITYRx_EL1
Res0 63:61
Field 60:56 Priority7
--
2.48.0
next prev parent reply other threads:[~2025-06-18 10:18 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-18 10:17 [PATCH v5 00/27] Arm GICv5: Host driver implementation Lorenzo Pieralisi
2025-06-18 10:17 ` [PATCH v5 01/27] dt-bindings: interrupt-controller: Add Arm GICv5 Lorenzo Pieralisi
2025-06-18 18:52 ` Rob Herring (Arm)
2025-06-18 10:17 ` [PATCH v5 02/27] arm64/sysreg: Add GCIE field to ID_AA64PFR2_EL1 Lorenzo Pieralisi
2025-06-18 10:17 ` [PATCH v5 03/27] arm64/sysreg: Add ICC_PPI_PRIORITY<n>_EL1 Lorenzo Pieralisi
2025-06-18 10:17 ` [PATCH v5 04/27] arm64/sysreg: Add ICC_ICSR_EL1 Lorenzo Pieralisi
2025-06-18 10:17 ` [PATCH v5 05/27] arm64/sysreg: Add ICC_PPI_HMR<n>_EL1 Lorenzo Pieralisi
2025-06-18 10:17 ` Lorenzo Pieralisi [this message]
2025-06-18 10:17 ` [PATCH v5 07/27] arm64/sysreg: Add ICC_PPI_{C/S}ACTIVER<n>_EL1 Lorenzo Pieralisi
2025-06-18 10:17 ` [PATCH v5 08/27] arm64/sysreg: Add ICC_PPI_{C/S}PENDR<n>_EL1 Lorenzo Pieralisi
2025-06-18 10:17 ` [PATCH v5 09/27] arm64/sysreg: Add ICC_CR0_EL1 Lorenzo Pieralisi
2025-06-18 10:17 ` [PATCH v5 10/27] arm64/sysreg: Add ICC_PCR_EL1 Lorenzo Pieralisi
2025-06-18 10:17 ` [PATCH v5 11/27] arm64/sysreg: Add ICC_IDR0_EL1 Lorenzo Pieralisi
2025-06-18 10:17 ` [PATCH v5 12/27] arm64/sysreg: Add ICH_HFGRTR_EL2 Lorenzo Pieralisi
2025-06-18 10:17 ` [PATCH v5 13/27] arm64/sysreg: Add ICH_HFGWTR_EL2 Lorenzo Pieralisi
2025-06-18 10:17 ` [PATCH v5 14/27] arm64/sysreg: Add ICH_HFGITR_EL2 Lorenzo Pieralisi
2025-06-18 10:17 ` [PATCH v5 15/27] arm64: Disable GICv5 read/write/instruction traps Lorenzo Pieralisi
2025-06-18 10:17 ` [PATCH v5 16/27] arm64: cpucaps: Rename GICv3 CPU interface capability Lorenzo Pieralisi
2025-06-18 10:17 ` [PATCH v5 17/27] arm64: cpucaps: Add GICv5 CPU interface (GCIE) capability Lorenzo Pieralisi
2025-06-18 10:17 ` [PATCH v5 18/27] arm64: smp: Support non-SGIs for IPIs Lorenzo Pieralisi
2025-06-25 18:53 ` Marc Zyngier
2025-06-18 10:17 ` [PATCH v5 19/27] arm64: Add support for GICv5 GSB barriers Lorenzo Pieralisi
2025-06-18 10:17 ` [PATCH v5 20/27] irqchip/gic-v5: Add GICv5 PPI support Lorenzo Pieralisi
2025-06-18 10:17 ` [PATCH v5 21/27] irqchip/gic-v5: Add GICv5 IRS/SPI support Lorenzo Pieralisi
2025-06-18 10:17 ` [PATCH v5 22/27] irqchip/gic-v5: Add GICv5 LPI/IPI support Lorenzo Pieralisi
2025-06-18 10:17 ` [PATCH v5 23/27] irqchip/gic-v5: Enable GICv5 SMP booting Lorenzo Pieralisi
2025-06-18 10:17 ` [PATCH v5 24/27] irqchip/gic-v5: Add GICv5 ITS support Lorenzo Pieralisi
2025-06-18 19:56 ` Lorenzo Pieralisi
2025-06-20 19:18 ` Thomas Gleixner
2025-06-23 7:43 ` Lorenzo Pieralisi
2025-06-23 9:26 ` Lorenzo Pieralisi
2025-06-23 19:04 ` Thomas Gleixner
2025-06-18 10:17 ` [PATCH v5 25/27] irqchip/gic-v5: Add GICv5 IWB support Lorenzo Pieralisi
2025-06-18 10:17 ` [PATCH v5 26/27] docs: arm64: gic-v5: Document booting requirements for GICv5 Lorenzo Pieralisi
2025-06-18 10:17 ` [PATCH v5 27/27] arm64: Kconfig: Enable GICv5 Lorenzo Pieralisi
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