From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D335026B0B2; Thu, 26 Jun 2025 10:28:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750933708; cv=none; b=DIDIJIvnQS7PvDrl0lUCoZ91qKeK0JkNl933lKZjqdtyJTZUloEIWnTdLgPr6LKNdYuXpAVUHRG7+4sKaMP3uX/SxxJBKxCrddaeRL1CmmISAgdjDSzVvcl1a1haVUVjIx5YUkRTsqea1X0XR9A3R/YDKDI/ymrJ0Kuf2irln6Q= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750933708; c=relaxed/simple; bh=zmaOaCaGrNIca6PHGvZg6PX26YBuJXmvB34xbCTXI6E=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Lrd/SLIIR86I8uRJNAfrVf/Q6MMg2AR1Avpzhdu4c89NVk7mvBeAeq1/OJTorCrutNTliBbTE7wp7ps5H9hqqj1eYQ7qeo2CkVYUv9LpiCQYy/sgT+DKBcOWfMNgVfHAhX1qisecyqbabvM9BSMM+bcuXzuxToMzssGpX0W1n6g= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Pcx/NYZ4; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Pcx/NYZ4" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 06B2FC4CEEB; Thu, 26 Jun 2025 10:28:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1750933708; bh=zmaOaCaGrNIca6PHGvZg6PX26YBuJXmvB34xbCTXI6E=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=Pcx/NYZ4/UYNk55nyWjqZAHi/WTVDwBLCoZRKGiqZC8+/GRPbMO2KILXnKikNiuNi nI5t7lWrdefmsuEzuKqV94Ip6aeM8r1wWkQuWIgZnW03YmT1JJ93M44aoHTP+c/teg CZ47UwWUEt3GwY8fDhII/QNURhaqRbxw/cjZKyM42LhcCuOnOYNhx+gfr/qkTyTOls xl3kr4eOOOSgrVlNa/aGtZ0MBOrIxI+YQ5XiGkMsNLYnK4Hzj6TaUOS50mCN63Nvco Xx6KDXyezaW9LGr7/eEkXlkleqwldlAiavSisf2/CeVtIQX48InhvpiHFpfqCr+RpN kqCaiOIrzesCg== From: Lorenzo Pieralisi Date: Thu, 26 Jun 2025 12:26:14 +0200 Subject: [PATCH v6 23/31] irqchip/gic-v5: Enable GICv5 SMP booting Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20250626-gicv5-host-v6-23-48e046af4642@kernel.org> References: <20250626-gicv5-host-v6-0-48e046af4642@kernel.org> In-Reply-To: <20250626-gicv5-host-v6-0-48e046af4642@kernel.org> To: Marc Zyngier , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Will Deacon Cc: Arnd Bergmann , Sascha Bischoff , Jonathan Cameron , Timothy Hayes , Bjorn Helgaas , "Liam R. Howlett" , Peter Maydell , Mark Rutland , Jiri Slaby , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-pci@vger.kernel.org, Lorenzo Pieralisi X-Mailer: b4 0.15-dev-6f78e Set up IPIs by allocating IPI IRQs for all cpus and call into arm64 core code to initialise IPIs IRQ descriptors and request the related IRQ. Implement hotplug callback to enable interrupts on a cpu and register the cpu with an IRS. Co-developed-by: Sascha Bischoff Signed-off-by: Sascha Bischoff Co-developed-by: Timothy Hayes Signed-off-by: Timothy Hayes Signed-off-by: Lorenzo Pieralisi Cc: Thomas Gleixner Cc: Marc Zyngier --- drivers/irqchip/irq-gic-v5.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/drivers/irqchip/irq-gic-v5.c b/drivers/irqchip/irq-gic-v5.c index fab9178edaf8..ab576c632eaa 100644 --- a/drivers/irqchip/irq-gic-v5.c +++ b/drivers/irqchip/irq-gic-v5.c @@ -5,6 +5,7 @@ #define pr_fmt(fmt) "GICv5: " fmt +#include #include #include #include @@ -909,6 +910,8 @@ static void gicv5_cpu_enable_interrupts(void) write_sysreg_s(cr0, SYS_ICC_CR0_EL1); } +static int base_ipi_virq; + static int gicv5_starting_cpu(unsigned int cpu) { if (WARN(!gicv5_cpuif_has_gcie(), @@ -920,6 +923,22 @@ static int gicv5_starting_cpu(unsigned int cpu) return gicv5_irs_register_cpu(cpu); } +static void __init gicv5_smp_init(void) +{ + unsigned int num_ipis = GICV5_IPIS_PER_CPU * nr_cpu_ids; + + cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_GIC_STARTING, + "irqchip/arm/gicv5:starting", + gicv5_starting_cpu, NULL); + + base_ipi_virq = irq_domain_alloc_irqs(gicv5_global_data.ipi_domain, + num_ipis, NUMA_NO_NODE, NULL); + if (WARN(base_ipi_virq <= 0, "IPI IRQ allocation was not successful")) + return; + + set_smp_ipi_range_percpu(base_ipi_virq, GICV5_IPIS_PER_CPU, nr_cpu_ids); +} + static void __init gicv5_free_domains(void) { if (gicv5_global_data.ppi_domain) @@ -1041,6 +1060,8 @@ static int __init gicv5_of_init(struct device_node *node, struct device_node *pa if (ret) goto out_int; + gicv5_smp_init(); + return 0; out_int: -- 2.48.0