From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 038EF25A35D; Thu, 26 Jun 2025 10:26:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750933619; cv=none; b=hpGuYEdDxxRDRZ92PDkkswDayKdPem/z31Z7ZgOCcVoerhEco3r7ugYEaZ0gtmgx4zK3xufMEoUCr2ggaob3H7hHJH0EdrQsCV+UM72ZgkBVVT76nJ6m0Ja/a53cDJ926yBbnpHO7zdkBaQlCfeLiPoVsGoWGLlz+sACq7JpOWw= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750933619; c=relaxed/simple; bh=wOLCrj/LhBFOilZTNOo8abVRncFumnr3LXRp84lKrug=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=qYBYgDprAgoKeivA7smxyYwa7rGiq/8YxW3wAlXj216Y3b/UKcTwEklCz0P7+kir8PtCqpYI5892o/V/06tVtKWr8WIYEX1oR8c+0SXOx74KmKi5VbmbBO3AAq/Dslu6nzaW1evx2A+1kj4XlaWunnMk/97gI10l5KjgANGDvkg= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=brOBneHu; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="brOBneHu" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 1A85FC4CEEE; Thu, 26 Jun 2025 10:26:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1750933618; bh=wOLCrj/LhBFOilZTNOo8abVRncFumnr3LXRp84lKrug=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=brOBneHuTe8sb9mw+IDgzfSXEY6/qhTOuUV0HN8q5futOSDO1i+vQngod0x+/Dqbd AL7oPrEopVvL618yRPsPuLUc80h8uPJoHwxAChR6cOn5/ajyVUKJwdlFAxSR5Uc8/g Soj3bEmLrp33XmOK231MqX+tjk9K7Me8lWGpJkdyPKFjM9CxK0GSC0jBZn7I/tx5/H Fp7FSdhSprL6pez6W983qC6SzJyL6wUkIQrxiKyephZQKzCuzAH/4rDGz6l7Xdgd1c WWh8kXsRTSMcxHC5S5YyhlToohNglkAvROOyQOdLTWWwBDzgVGzEccC0RMRV+IzZin VFfSSlJmpzc+A== From: Lorenzo Pieralisi Date: Thu, 26 Jun 2025 12:25:57 +0200 Subject: [PATCH v6 06/31] arm64/sysreg: Add ICC_PPI_ENABLER_EL1 Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20250626-gicv5-host-v6-6-48e046af4642@kernel.org> References: <20250626-gicv5-host-v6-0-48e046af4642@kernel.org> In-Reply-To: <20250626-gicv5-host-v6-0-48e046af4642@kernel.org> To: Marc Zyngier , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Will Deacon Cc: Arnd Bergmann , Sascha Bischoff , Jonathan Cameron , Timothy Hayes , Bjorn Helgaas , "Liam R. Howlett" , Peter Maydell , Mark Rutland , Jiri Slaby , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-pci@vger.kernel.org, Lorenzo Pieralisi X-Mailer: b4 0.15-dev-6f78e Add ICC_PPI_ENABLER_EL1 registers sysreg description. Signed-off-by: Lorenzo Pieralisi Reviewed-by: Jonathan Cameron Cc: Will Deacon Cc: Catalin Marinas Cc: Marc Zyngier --- arch/arm64/tools/sysreg | 75 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 75 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 7f096efee4e7..728223df482d 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -3113,6 +3113,81 @@ Field 1 Enabled Field 0 F EndSysreg +SysregFields ICC_PPI_ENABLERx_EL1 +Field 63 EN63 +Field 62 EN62 +Field 61 EN61 +Field 60 EN60 +Field 59 EN59 +Field 58 EN58 +Field 57 EN57 +Field 56 EN56 +Field 55 EN55 +Field 54 EN54 +Field 53 EN53 +Field 52 EN52 +Field 51 EN51 +Field 50 EN50 +Field 49 EN49 +Field 48 EN48 +Field 47 EN47 +Field 46 EN46 +Field 45 EN45 +Field 44 EN44 +Field 43 EN43 +Field 42 EN42 +Field 41 EN41 +Field 40 EN40 +Field 39 EN39 +Field 38 EN38 +Field 37 EN37 +Field 36 EN36 +Field 35 EN35 +Field 34 EN34 +Field 33 EN33 +Field 32 EN32 +Field 31 EN31 +Field 30 EN30 +Field 29 EN29 +Field 28 EN28 +Field 27 EN27 +Field 26 EN26 +Field 25 EN25 +Field 24 EN24 +Field 23 EN23 +Field 22 EN22 +Field 21 EN21 +Field 20 EN20 +Field 19 EN19 +Field 18 EN18 +Field 17 EN17 +Field 16 EN16 +Field 15 EN15 +Field 14 EN14 +Field 13 EN13 +Field 12 EN12 +Field 11 EN11 +Field 10 EN10 +Field 9 EN9 +Field 8 EN8 +Field 7 EN7 +Field 6 EN6 +Field 5 EN5 +Field 4 EN4 +Field 3 EN3 +Field 2 EN2 +Field 1 EN1 +Field 0 EN0 +EndSysregFields + +Sysreg ICC_PPI_ENABLER0_EL1 3 0 12 10 6 +Fields ICC_PPI_ENABLERx_EL1 +EndSysreg + +Sysreg ICC_PPI_ENABLER1_EL1 3 0 12 10 7 +Fields ICC_PPI_ENABLERx_EL1 +EndSysreg + SysregFields ICC_PPI_PRIORITYRx_EL1 Res0 63:61 Field 60:56 Priority7 -- 2.48.0