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([82.78.167.83]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ae3f66d9215sm194703766b.2.2025.07.04.09.14.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jul 2025 09:14:47 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: bhelgaas@google.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, catalin.marinas@arm.com, will@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de, lizhi.hou@amd.com Cc: claudiu.beznea@tuxon.dev, linux-pci@vger.kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, Claudiu Beznea , Wolfram Sang Subject: [PATCH v3 6/9] arm64: dts: renesas: r9a08g045s33: Add PCIe node Date: Fri, 4 Jul 2025 19:14:06 +0300 Message-ID: <20250704161410.3931884-7-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250704161410.3931884-1-claudiu.beznea.uj@bp.renesas.com> References: <20250704161410.3931884-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Claudiu Beznea The RZ/G3S SoC has a variant (R9A08G045S33) which support PCIe. Add the PCIe node. Tested-by: Wolfram Sang Signed-off-by: Claudiu Beznea --- Changes in v3: - collected tags - changed the ranges flags Changes in v2: - updated the dma-ranges to reflect the SoC capability; added a comment about it. - updated clock-names, interrupt names - dropped legacy-interrupt-controller node - added interrupt-controller property - moved renesas,sysc at the end of the node to comply with DT coding style arch/arm64/boot/dts/renesas/r9a08g045s33.dtsi | 60 +++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a08g045s33.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045s33.dtsi index 3351f26c7a2a..cff36e873e59 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g045s33.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g045s33.dtsi @@ -12,3 +12,63 @@ / { compatible = "renesas,r9a08g045s33", "renesas,r9a08g045"; }; + +&soc { + pcie: pcie@11e40000 { + compatible = "renesas,r9a08g045s33-pcie"; + reg = <0 0x11e40000 0 0x10000>; + ranges = <0x02000000 0 0x30000000 0 0x30000000 0 0x8000000>; + /* Map all possible DRAM ranges (4 GB). */ + dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0x1 0x0>; + bus-range = <0x0 0xff>; + clocks = <&cpg CPG_MOD R9A08G045_PCI_ACLK>, + <&cpg CPG_MOD R9A08G045_PCI_CLKL1PM>; + clock-names = "aclk", "pm"; + resets = <&cpg R9A08G045_PCI_ARESETN>, + <&cpg R9A08G045_PCI_RST_B>, + <&cpg R9A08G045_PCI_RST_GP_B>, + <&cpg R9A08G045_PCI_RST_PS_B>, + <&cpg R9A08G045_PCI_RST_RSM_B>, + <&cpg R9A08G045_PCI_RST_CFG_B>, + <&cpg R9A08G045_PCI_RST_LOAD_B>; + reset-names = "aresetn", "rst_b", "rst_gp_b", "rst_ps_b", + "rst_rsm_b", "rst_cfg_b", "rst_load_b"; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "serr", "serr_cor", "serr_nonfatal", + "serr_fatal", "axi_err", "inta", + "intb", "intc", "intd", "msi", + "link_bandwidth", "pm_pme", "dma", + "pcie_evt", "msg", "all"; + #interrupt-cells = <1>; + interrupt-controller; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie 0 0 0 0>, /* INT A */ + <0 0 0 2 &pcie 0 0 0 1>, /* INT B */ + <0 0 0 3 &pcie 0 0 0 2>, /* INT C */ + <0 0 0 4 &pcie 0 0 0 3>; /* INT D */ + device_type = "pci"; + num-lanes = <1>; + #address-cells = <3>; + #size-cells = <2>; + power-domains = <&cpg>; + vendor-id = <0x1912>; + device-id = <0x0033>; + renesas,sysc = <&sysc>; + status = "disabled"; + }; +}; -- 2.43.0