Linux PCI subsystem development
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From: Bjorn Helgaas <helgaas@kernel.org>
To: Manivannan Sadhasivam <mani@kernel.org>
Cc: "Niklas Cassel" <cassel@kernel.org>,
	"Jingoo Han" <jingoohan1@gmail.com>,
	"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
	"Krzysztof Wilczyński" <kwilczynski@kernel.org>,
	"Rob Herring" <robh@kernel.org>,
	"Bjorn Helgaas" <bhelgaas@google.com>,
	"Wilfred Mallawa" <wilfred.mallawa@wdc.com>,
	"Damien Le Moal" <dlemoal@kernel.org>,
	"Laszlo Fiat" <laszlo.fiat@proton.me>,
	linux-pci@vger.kernel.org
Subject: Re: [PATCH v4 5/7] PCI: dwc: Ensure that dw_pcie_wait_for_link() waits 100 ms after link up
Date: Mon, 7 Jul 2025 18:01:39 -0500	[thread overview]
Message-ID: <20250707230139.GA2122052@bhelgaas> (raw)
In-Reply-To: <hhyxhxvohmeqzjdu3amabcpf3e4ufi4ps5xd2uia4ea6i2u5oj@sxyjavqyqc7m>

On Wed, Jul 02, 2025 at 08:17:44PM +0530, Manivannan Sadhasivam wrote:
> On Wed, Jul 02, 2025 at 11:43:11AM GMT, Niklas Cassel wrote:
> > On Tue, Jul 01, 2025 at 11:38:44AM -0500, Bjorn Helgaas wrote:
> > > > 
> > > > No. The PERST# delay should be handled by the glue drivers since
> > > > they are the ones controlling the PERST# line. Doing an
> > > > unconditional wait for both the cases in DWC core, seems wrong to
> > > > me.
> > > 
> > > It ends up being a little bit weird that the delay is in the DWC core
> > > (dw_pcie_wait_for_link()) for ports that support fast links, and in
> > > the glue drivers otherwise.  It would be easier to verify and maintain
> > > if the delay were always in the DWC core.
> > > 
> > > If we had a dw_pcie_host_ops callback for PERST# deassertion, the
> > > delay could be in the DWC core, but I don't know if there's enough
> > > consistency across drivers for that to be practical.
> > 
> > Currently, there is not much consistency between the glue drivers,
> > so adding a DWC core API to assert/deassert PERST# sounds like a
> > good idea to me. The callback could even be supplied a struct
> > gpio_desc pointer.
> 
> +1 for consolidating the PERST# handling. But just FYI, I'm going to
> move the PERST# deassert handling from controller drivers to pwrctrl
> drivers as once pwrctrl drivers are used to control the power
> supplies, they should control PERST# as well. Currently, this is the
> missing piece for pwrctrl framework.
> 
> Also, we cannot entirely get rid of the PERST# handling in
> controller drivers, since they need to assert PERST# before
> resetting the RC during init.

I thought pwrctrl was optional.  The PERST# management is not
optional, is it?

Bjorn

  parent reply	other threads:[~2025-07-07 23:01 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-06-25 10:23 [PATCH v4 0/7] PCI: dwc: Do not enumerate bus before endpoint devices are ready Niklas Cassel
2025-06-25 10:23 ` [PATCH v4 1/7] PCI: Rename PCIE_RESET_CONFIG_DEVICE_WAIT_MS to PCIE_RESET_CONFIG_WAIT_MS Niklas Cassel
2025-06-25 10:23 ` [PATCH v4 2/7] PCI: rockchip-host: Use macro PCIE_RESET_CONFIG_WAIT_MS Niklas Cassel
2025-06-25 10:23 ` [PATCH v4 3/7] PCI: dw-rockchip: Wait PCIE_RESET_CONFIG_WAIT_MS after link-up IRQ Niklas Cassel
2025-06-25 10:23 ` [PATCH v4 4/7] PCI: qcom: " Niklas Cassel
2025-06-25 10:23 ` [PATCH v4 5/7] PCI: dwc: Ensure that dw_pcie_wait_for_link() waits 100 ms after link up Niklas Cassel
2025-06-30 20:19   ` Bjorn Helgaas
2025-07-01 11:55     ` Niklas Cassel
2025-07-01 13:01       ` Manivannan Sadhasivam
2025-07-01 16:38         ` Bjorn Helgaas
2025-07-02  9:43           ` Niklas Cassel
2025-07-02 14:47             ` Manivannan Sadhasivam
2025-07-02 16:17               ` Niklas Cassel
2025-07-07  7:48                 ` Manivannan Sadhasivam
2025-07-07 11:56                   ` Niklas Cassel
2025-07-08  7:49                     ` Manivannan Sadhasivam
2025-07-07 23:01               ` Bjorn Helgaas [this message]
2025-06-25 10:23 ` [PATCH v4 6/7] PCI: Move link up wait time and max retries macros to pci.h Niklas Cassel
2025-06-25 10:23 ` [PATCH v4 7/7] PCI: Reduce PCIE_LINK_WAIT_SLEEP_MS Niklas Cassel
2025-06-25 13:29 ` [PATCH v4 0/7] PCI: dwc: Do not enumerate bus before endpoint devices are ready Manivannan Sadhasivam

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