From: Ziyue Zhang <ziyue.zhang@oss.qualcomm.com>
To: andersson@kernel.org, konradybcio@kernel.org, robh@kernel.org,
krzk+dt@kernel.org, conor+dt@kernel.org, jingoohan1@gmail.com,
mani@kernel.org, lpieralisi@kernel.org, kwilczynski@kernel.org,
bhelgaas@google.com, johan+linaro@kernel.org, vkoul@kernel.org,
kishon@kernel.org, neil.armstrong@linaro.org,
abel.vesa@linaro.org, kw@linux.com
Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org,
linux-phy@lists.infradead.org, qiang.yu@oss.qualcomm.com,
quic_krichai@quicinc.com, quic_vbadigan@quicinc.com,
Ziyue Zhang <ziyue.zhang@oss.qualcomm.com>
Subject: [PATCH v4 0/3] Add Equalization Settings for 8.0 GT/s and Add PCIe Lane Equalization Preset Properties for 8.0 GT/s and 16.0 GT/s
Date: Mon, 14 Jul 2025 16:21:07 +0800 [thread overview]
Message-ID: <20250714082110.3890821-1-ziyue.zhang@oss.qualcomm.com> (raw)
This series adds add equalization settings for 8.0 GT/s, and add PCIe lane equalization
preset properties for 8.0 GT/s and 16.0 GT/s for sa8775p ride platform, which fix AER
errors.
While equalization settings for 16 GT/s have already been set, this update adds the
required equalization settings for PCIe operating at 8.0 GT/s, including the
configuration of shadow registers, ensuring optimal performance and stability.
The DT change for sa8775p add PCIe lane equalization preset properties for 8 GT/s
and 16 GT/s data rates used in lane equalization procedure.
Signed-off-by: Ziyue Zhang <ziyue.zhang@oss.qualcomm.com>
Changes in v4:
- Bail out early if the link speed > 16 GT/s and use pci->max_link_speed directly (Mani)
- Fix the build warning. (Bjorn)
- Link to v3: https://lore.kernel.org/all/8ccd3731-8dbc-4972-a79a-ba78e90ec4a8@quicinc.com/
Changes in v3:
- Delte TODO tag and warn print in pcie-qcom-common.c. (Bjorn)
- Refined the commit message for better readability. (Bjorn)
- Link to v2: https://lore.kernel.org/all/20250611100319.464803-1-quic_ziyuzhan@quicinc.com/
Changes in v2:
- Update code in pcie-qcom-common.c make it easier to read. (Neil)
- Fix the compile error.
- Link to v1: https://lore.kernel.org/all/20250604091946.1890602-1-quic_ziyuzhan@quicinc.com
Ziyue Zhang (3):
PCI: qcom: Add equalization settings for 8.0 GT/s
PCI: qcom: fix macro typo for CURSOR
arm64: dts: qcom: sa8775p: Add PCIe lane equalization preset
properties
arch/arm64/boot/dts/qcom/sa8775p.dtsi | 6 +++
drivers/pci/controller/dwc/pcie-designware.h | 5 +-
drivers/pci/controller/dwc/pcie-qcom-common.c | 54 ++++++++++---------
drivers/pci/controller/dwc/pcie-qcom-common.h | 2 +-
drivers/pci/controller/dwc/pcie-qcom-ep.c | 6 +--
drivers/pci/controller/dwc/pcie-qcom.c | 6 +--
6 files changed, 45 insertions(+), 34 deletions(-)
base-commit: 58ba80c4740212c29a1cf9b48f588e60a7612209
--
2.34.1
next reply other threads:[~2025-07-14 8:21 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-07-14 8:21 Ziyue Zhang [this message]
2025-07-14 8:21 ` [PATCH v4 1/3] PCI: qcom: Add equalization settings for 8.0 GT/s Ziyue Zhang
2025-07-14 8:21 ` [PATCH v4 2/3] PCI: qcom: fix macro typo for CURSOR Ziyue Zhang
2025-07-14 8:21 ` [PATCH v4 3/3] arm64: dts: qcom: sa8775p: Add PCIe lane equalization preset properties Ziyue Zhang
2025-08-12 8:32 ` [PATCH v4 0/3] Add Equalization Settings for 8.0 GT/s and Add PCIe Lane Equalization Preset Properties for 8.0 GT/s and 16.0 GT/s Ziyue Zhang
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